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DM504 Datasheet(PDF) 117 Page - Texas Instruments |
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DM504 Datasheet(HTML) 117 Page - Texas Instruments |
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117 / 211 page  cs sclk rtclk d[0] d[3:1] Bit n-1 Bit n-2 Bit 1 Bit 0 PHA=0 POL=0 POL=0 Command Command Read Data Read Data Bit 1 Bit 0 Read Data Read Data Q4 Q7 Q9 Q2 Q3 Q1 Q6 Q5 SPRS85v_TIMING_OSPI1_02 Q12 Q13 Q12 Q13 Q12 Q13 Q12 Q13 117 DM504 www.ti.com SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated Figure 5-24. QSPI Read (Clock Mode 0) CAUTION The IO Timings provided in this section are only valid when all QSPI Chip Selects used in a system are configured to use the same Clock Mode (either Clock Mode 0 or Clock Mode 3). Table 5-44. Timing Requirements for QSPI No PARAMETER DESCRIPTION Mode MIN MAX UNIT 12 tsu(D-RTCLK) Setup time, d[3:0] valid before falling rtclk edge Default Timing Mode, Clock Mode 0 2.9 ns tsu(D-SCLK) Setup time, d[3:0] valid before falling sclk edge Default Timing Mode, Clock Mode 3 5.7 ns |
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