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DM504 Datasheet(PDF) 126 Page - Texas Instruments |
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DM504 Datasheet(HTML) 126 Page - Texas Instruments |
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126 / 211 page  126 DM504 SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 www.ti.com Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated CAUTION The IO timings provided in this section are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 5-52. In Table 5-52 are presented the specific groupings of signals (IOSET) for use with McASP1. Table 5-52. McASP1 IOSETs SIGNALS IOSET1 IOSET2 IOSET3 BALL MUX BALL MUX BALL MUX mcasp1_aclkx T14 1 T14 1 T14 1 mcasp1_fsx U13 1 U13 1 U13 1 mcasp1_aclkr U12 1 mcasp1_fsr T12 1 mcasp1_axr0 R13 1 R13 1 R13 1 mcasp1_axr1 R12 1 R12 1 R12 1 mcasp1_axr2 U11 1 mcasp1_axr3 P12 1 mcasp1_axr4 T11 1 mcasp1_axr5 R11 1 mcasp1_axr6 R10 1 mcasp1_axr7 T10 1 mcasp1_axr8 T9 1 T9 1 U11 4 mcasp1_axr9 U9 1 U9 1 P12 4 mcasp1_axr10 R9 1 T11 4 mcasp1_axr11 T8 1 R11 4 mcasp1_axr12 U7 1 R10 4 mcasp1_axr13 R8 1 T10 4 mcasp1_axr14 R7 1 T4 4 mcasp1_axr15 T7 1 U3 4 5.9.6.12 DCAN and MCAN 5.9.6.12.1 DCAN The device provides one DCAN interface for supporting distributed realtime control with a high level of security. The DCAN interface implements the following features: • Supports CAN protocol version 2.0 part A, B • Bit rates up to 1 MBit/s • 64 message objects • Individual identifier mask for each message object • Programmable FIFO mode for message objects • Programmable loop-back modes for self-test operation • Suspend mode for debug support • Automatic bus on after Bus-Off state by a programmable 32-bit timer • Message RAM single error correction and double error detection (SECDED) mechanism • Direct access to Message RAM during test mode • Support for two interrupt lines: Level 0 and Level 1, plus separate ECC interrupt line |
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