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DM504 Datasheet(PDF) 130 Page - Texas Instruments |
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DM504 Datasheet(HTML) 130 Page - Texas Instruments |
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130 / 211 page  rgmii _rxd[3:0] n (B) rgmii _rxctl n (B) rgmii _rxc n (A) 5 RXERR RXDV 1st Half-byte 2nd Half-byte RGRXD[7:4] RGRXD[3:0] 2 3 1 4 4 6 SPRS91v_GMAC_08 130 DM504 SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 www.ti.com Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated 5.9.6.13.2 GMAC RGMII Timings Table 5-58, Table 5-59 and Figure 5-31 present timing requirements for receive RGMIIn operation. Table 5-58. Timing Requirements for rgmiin_rxc - RGMIIn Operation NO. PARAMETER DESCRIPTION SPEED MIN MAX UNIT 1 tc(RXC) Cycle time, rgmiin_rxc 10 Mbps 360 440 ns 100 Mbps 36 44 ns 1000 Mbps 7.2 8.8 ns 2 tw(RXCH) Pulse duration, rgmiin_rxc high 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns 3 tw(RXCL) Pulse duration, rgmiin_rxc low 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns 4 tt(RXC) Transition time, rgmiin_rxc 10 Mbps 0.75 ns 100 Mbps 0.75 ns 1000 Mbps 0.75 ns Table 5-59. Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps NO. PARAMETER DESCRIPTION MIN MAX UNIT 5 tsu(RXD-RXCH) Setup time, receive selected signals valid before rgmiin_rxc high/low 1.15 ns 6 th(RXCH-RXD) Hold time, receive selected signals valid after rgmiin_rxc high/low 1.15 ns (1) For RGMII, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl. (2) RGMII0 requires that the 4 data pins rgmii0_rxd[3:0] and rgmii0_rxctl have their board propagation delays matched within 50pS of rgmii0_rxc. (3) RGMII1 requires that the 4 data pins rgmii1_rxd[3:0] and rgmii1_rxctl have their board propagation delays matched within 50pS of rgmii1_rxc. A. rgmiin_rxc must be externally delayed relative to the data and control pins. B. Data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc. Figure 5-31. GMAC Receive Interface Timing, RGMIIn operation |
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