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DM504 Datasheet(PDF) 133 Page - Texas Instruments |
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DM504 Datasheet(HTML) 133 Page - Texas Instruments |
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133 / 211 page  DS2 DS1 DS0 DS3 DS4 mmc_clk mmc_cmd mmc_dat[3:0] SPRS91v_MMC_02 DS2 DS1 DS0 DS6 DS5 DS8 DS7 mmc_clk mmc_cmd mmc_dat[3:0] SPRS91v_MMC_01 133 DM504 www.ti.com SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated Table 5-63. Switching Characteristics for MMC - SD/SDIO Default Speed Mode (continued) NO. PARAMETER DESCRIPTION MIN MAX UNIT DS2 tw(clkL) Pulse duration, mmc_clk low 0.5*P- 0.270 ns DS3 td(clkL-cmdV) Delay time, mmc_clk falling clock edge to mmc_cmd transition -14.93 14.93 ns DS4 td(clkL-dV) Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition -14.93 14.93 ns (1) P = output mmc_clk period in ns (2) i in [i:0] = 3 Figure 5-33. MMC/SD/SDIOj in - Default Speed - Receiver Mode Figure 5-34. MMC/SD/SDIOj in - Default Speed - Transmiter Mode 5.9.6.14.2 MMC, SD High Speed Figure 5-35, Figure 5-36, Table 5-64, and Table 5-65 present Timing requirements and Switching characteristics for MMC - SD and SDIO High speed in receiver and transmiter mode. Table 5-64. Timing Requirements for MMC - SD/SDIO High Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT HS3 tsu(cmdV-clkH) Setup time, mmc_cmd valid before mmc_clk rising clock edge 5.3 ns HS4 th(clkH-cmdV) Hold time, mmc_cmd valid after mmc_clk rising clock edge 2.6 ns HS7 tsu(dV-clkH) Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge 5.3 ns HS8 th(clkH-dV) Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge 2.6 ns |
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