AD9545 datasheet(155/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 155 of 157

In read mode, the master device (receiver) receives the last data

byte from the slave device (transmitter) but does not pull SDA

low during the ninth clock pulse (a nonacknowledge bit). By

receiving the nonacknowledge bit, the slave device knows that the

data transfer is finished and enters idle mode.

The master device then takes the data line low during the low

period before the 10th clock pulse, and high during the 10th

clock pulse to assert a stop condition.

A start condition can be used instead of a stop condition.

Furthermore, a start or stop condition can occur at any time,

and partially transferred bytes are discarded.

SDA

START CONDITION

STOP CONDITION

SCL

Figure 124. Start and Stop Conditions

3 TO 7

SDA

SCL

MSB

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

Figure 125. Acknowledge Bit

3 TO 7

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

SDA

SCL

MSB

Figure 126. Data Transfer Process (Master Write Mode, 2-Byte Transfer)

3 TO 7

ACK FROM

MASTER RECEIVER

NONACK FROM

MASTER RECEIVER

SDA

SCL

Figure 127. Data Transfer Process (Master Read Mode, 2-Byte Transfer), First Acknowledge From Slave

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