AD9554 datasheet(33/116 Pages) AD

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Data Sheet

AD9554

Rev. D | Page 33 of 116

THEORY OF OPERATION

XOA

XOB

REFA

REFB

REFC

REFD

÷2, ÷4, ÷8

×2

÷RA

÷RB

÷RC

÷RD

REFERENCE

MONITORS

AND

CROSSPOINT

MUX

SYSCLK

MULTIPLIER

REF

XTAL

SYSTEM

CLOCK

LOOP

FILTER

OUT1A

OUT1B

÷Q0_B

DPFD

CLAMP

NCO_0

FRAC0 ÷ MOD0

÷N0

÷M0

÷P0

PFD/CP

FREE RUN

TUNING

WORD

VCO_0

2424MHz TO 3132MHz

÷Q0_A

OUT0B

OUT0A

RESET

SCLK/SCL

SDIO/SDA

SDO

CONTROL

INTERFACE/LOGIC

AND

EEPROM INTERFACE

INPUT REFERENCE

FREQUENCY RANGE:

2kHz TO 1000MHz

PLL0

SAME DETAIL AS PLL0

VCO_1 RANGE = 3232MHz TO 3905MHz

OUT2A

OUT2B

OUT3A

OUT3B

SAME DETAIL AS PLL0

VCO_2 RANGE = 4842MHz TO 5650MHz

SAME DETAIL AS PLL0

VCO_3 RANGE = 4040MHz TO 4748MHz

PLL1

PLL2

PLL3

Figure 30. Detailed Block Diagram

OVERVIEW

The AD9554 provides clocking outputs that are directly related

in phase and frequency to the selected (active) reference but

with jitter characteristics governed by the system clock, the

DCO, and the analog output PLL (APLL). The AD9554 can be

thought of as four copies of the AD9557 inside one package,

with a 4:4 crosspoint controlling the reference inputs. The

AD9554 supports up to four reference inputs and input

frequencies ranging from 2 kHz to 1000 MHz. The cores of this

device are four digital phase-locked loops (DPLLs). Each DPLL

has a programmable digital loop filter that greatly reduces jitter

transferred from the active reference to the output, and these four

DPLLs operate completely independently of each other. The

AD9554 supports both manual and automatic holdover. While in

holdover, the AD9554 continues to provide an output as long as

the system clock is present. The holdover output frequency is a

time average of the output frequency history prior to the

transition to the holdover condition. The device offers manual

and automatic reference switchover capability if the active

reference is degraded or fails completely. The AD9554 also has

adaptive clocking capability that allows the user to dynamically

change the DPLL divide ratios while the DPLLs are locked.

The AD9554 includes a system clock multiplier, four DPLLs,

and four APLLs. The input signal goes first to the DPLL, which

performs the jitter cleaning and most of the frequency translation.

Each DPLL features a 30-bit DCO output that generates a signal

in the range of 283 MHz to 345 MHz.

The DCO output goes to the APLL, which multiplies the signal

up to a range of 2.4 GHz to 5.6 GHz. This signal is then sent to the

clock distribution section, which consists of a P divider cascaded

with 10-bit channel dividers (divide by 1 to divide by 1024).

The XOA and XOB inputs provide the input for the system

clock. These pins accept a reference clock in the 10 MHz to

268 MHz range or a 10 MHz to 50 MHz crystal connected

directly across the XOA and XOB inputs. The system clock

provides the clocks to the frequency monitors, the DPLLs, and

internal switching logic.

Each APLL on the AD9554 has two differential output drivers.

Each of the eight output drivers has a dedicated 10-bit

programmable post divider. Each differential driver operates up

to 1.25 GHz and is an HCSL driver with a 58 Ω internal

termination resistor on each leg. There are three drive strengths:



The 14 mA mode is used for HCSL and ac-coupled LVDS.

When used as an LVDS-compatible driver, it must be ac-

coupled and terminated with a 100 Ω resistor across the

differential pair.



The 28 mA mode produces a voltage swing and is compatible

with LVPECL. If LVPECL signal levels are required, the

designer must ac-couple the AD9554 output.



The 21 mA mode is halfway in between the two other

settings.

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