AD9554 datasheet(18/116 Pages) AD

18 / 116 page

AD9554

Data Sheet

Rev. D | Page 18 of 116

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

REFD

Differential

input

Complementary Reference D Input. Complementary signal to the input

provided on Pin 7 (REFD). This pin can be left floating if REFD is a single-ended

input or if REFD is not used.

REFA

Differential

input

Complementary Reference A Input. Complementary signal to the input

provided on Pin 12 (REFA). This pin can be left floating if REFA is a single-ended

input or if REFA is not used.

REFA

Differential

input

Reference A Input. This internally biased input is typically ac-coupled; when

configured in this manner, it can accept any differential signal with single-

ended swing up to the VDD power supply. If dc-coupled, the input can be

LVDS or single-ended CMOS provided that VIH ≤ VDD.

OUT0A

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL0 Complementary Output 0A. Complementary signal to the output

provided on Pin 16 (OUT0A).

OUT0A

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL0 Output 0A. This HCSL output can be configured as a LVDS- or LVPECL-

compatible output. LVPECL and LVDS levels can be achieved by ac-coupling

and using the Thevenin equivalent termination as described in the

Input/Output Termination Recommendations section.

OUT0B

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL0 Complementary Output 0B. Complementary signal to the output

provided on Pin 19 (OUT0A).

OUT0B

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL0 Output 0B. This HCSL output can be configured as a LVDS- or LVPECL-

compatible output. LVPECL and LVDS levels can be achieved by ac-coupling

and using the Thevenin equivalent termination as described in the

Input/Output Termination Recommendations section.

LDO_0

LDO bypass

APLL_0 Loop Filter Voltage Regulator. Connect a 0.22 μF capacitor from this pin

to ground. This pin is also the ac ground reference for the integrated APLL_0

external loop filter.

LF_0

I/O

Loop filter for

APLL_0

Loop Filter Node for the APLL_0. Connect an external 15 nF capacitor from this

pin to Pin 22 (LDO_0).

I/O

1.5 V/1.8 V

CMOS

Configurable Input/Output Pin. This pin is used for status and control of the

AD9554. At power-up and reset this pin controls whether or not the M1 and

M2 pins are used for the serial port connection to the optional external

EEPROM. See the Multifunction Pins at Reset/Power-Up section for more

information about internal 100 kΩ pull-up or pull-down resistors. This pin is on

the VDD power domain, and the logic high voltage for this pin matches the

voltage of the VDD pins.

SDO

CMOS

Serial Data Output (SDO). In 4-wire SPI mode, this pin is used for reading serial

data. The VIH/VOH of this pin tracks the VDD_SP power supply, which can be

1.5 V, 1.8 V, or 2.5 V.

SDIO/SDA

I/O

CMOS

In SPI mode, this is the serial data input/output (SDIO) pin. In 4-wire SPI mode,

data is written via this pin. In 3-wire SPI mode, data reads and writes both

occur on this pin. In I2C mode, this is the serial data pin (SDA) pin. There is no

internal pull-up/pull-down resistor on this pin. The VIH/VOH of this pin tracks the

VDD_SP power supply, which can be 1.5 V, 1.8 V, or 2.5 V.

SCLK/SCL

CMOS

In SPI mode, this is the serial programming clock (SCLK) pin. In I2C mode, this is

the serial clock pin (SCL). The VIH/VOH of this pin tracks the VDD_SP power

supply, which can be 1.5 V, 1.8 V, or 2.5 V.

CMOS

Chip Select in SPI Mode (CS). Active low input. When programming a device in

SPI, this pin must be held low. In systems where more than one AD9554 is

present, this pin enables individual programming of each AD9554. This pin has

an internal 10 kΩ pull-up resistor. The VIH of this pin tracks the VDD_SP power

supply, which can be 1.5 V, 1.8 V, or 2.5 V.

VDD_SP

Power

Serial Port Power Supply. The power supply can be 1.5 V, 1.8 V, or 2.5 V. If this

pin is at the same voltage as VDD, it can be connected to VDD pins.

RESET

1.5 V/1.8 V/

2.5 V CMOS

Chip Reset. When this active low pin is asserted, the chip goes into reset. This

pin has an internal 50 kΩ pull-up resistor. The VIH of this pin tracks the VDD_SP

power supply, which can be 1.5 V, 1.8 V, or 2.5 V.

AD9554 Datasheet(PDF) 18 Page - Analog Devices

AD9554 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL