AD9554 datasheet(8/116 Pages) AD

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AD9554

Data Sheet

Rev. D | Page 8 of 116

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SINGLE-ENDED MODE

DC-coupled

Frequency Range (CMOS)

0.002

300

MHz

Minimum Input Slew Rate

Minimum limit imposed for jitter performance

DPLL Loop Bandwidth = 50 Hz

V/μs

DPLL Loop Bandwidth = 4 kHz

175

V/μs

Maximum loop bandwidth is fPFD/50

Input Voltage High, VIH

VDD − 0.5

Input Voltage Low, VIL

0.5

Input Resistance

kΩ

Input Capacitance

Minimum Pulse Width High

1.5

Minimum Pulse Width Low

1.5

REFERENCE MONITORS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE MONITORS

Reference Monitor

Loss of Reference Detection Time

1.15

DPLL PFD period

Nominal phase detector period = R/fREF, where R is the

frequency division factor determined by the R divider,

and fREF is the frequency of the active reference

Frequency Out-of Range Limits

105

Δf/fREF (ppm)

Programmable (lower bound subject to quality of the

system clock [SYSCLK]); SYSCLK accuracy must be less

than the lower bound

Validation Timer

0.001

65.535

sec

Programmable in 1 ms increments

REFERENCE SWITCHOVER SPECIFICATIONS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

MAXIMUM OUTPUT PHASE PERTURBATION

(PHASE BUILD-OUT SWITCHOVER)

Assumes a jitter-free reference; satisfies

Telcordia GR-1244-CORE requirements; base

loop filter selection bit set to 1b or all active

references

50 Hz DPLL Loop Bandwidth

High phase margin mode; 19.44 MHz to

174.70308 MHz; DPLL bandwidth = 50 Hz;

49.152 MHz signal generator used for system

clock source

Peak

±20

±130

Steady State

±20

±130

Time Required to Switch to a New Reference

Phase Build-Out Switchover

DPLL

PFD

period

Calculated using the nominal phase detector

period (NPDP = R/fREF); the total time required

is the time plus the reference validation time,

plus the time required to lock to the new

reference

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