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AD9554 Datasheet(PDF) 73 Page - Analog Devices

Part # AD9554
Description  Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
PDF  116 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9554 Datasheet(HTML) 73 Page - Analog Devices

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Data Sheet
AD9554
Rev. D | Page 73 of 116
Address
Bits
Bit Name
Description
0x010D
[7:0]
Watchdog timer
Watchdog timer, Bits[7:0]. The watchdog timer stops when this register is written and
restarts on the next IO_UPDATE (Register 0x000F = 0x01). Default: 0x00 (0x0000 =
disabled). The units are in milliseconds.
0x010E
[7:0]
Watchdog timer, Bits[15:8]. The watchdog timer stops when this register is written and
restarts on the next IO_UPDATE (Register 0x000F = 0x01). Default: 0x00.
IRQ MASK (REGISTER 0x010F TO REGISTER 0x011F)
The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (0x0D08 to 0x0D16). When set to
Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is
Logic 0, which prevents the IRQ monitor from detecting any internal interrupts.
Table 41. IRQ Mask for SYSCLK, Watchdog Timer, and EEPROM
Address
Bits
Bit Name
Description
0x010F
7
SYSCLK unlocked
Enables IRQ to indicate that the system clock has gone from locked to unlocked.
6
SYSCLK stable
Enables IRQ to indicate that the system clock has gone from unstable to stable.
5
SYSCLK locked
Enables IRQ to indicate that the system clock has gone from unlocked to locked.
4
SYSCLK calibration
ended
Enables IRQ to indicate that the system clock calibration sequence has ended.
3
SYSCLK calibration
started
Enables IRQ to indicate that the system clock calibration sequence has started.
2
Watchdog timer
Enables IRQ to indicate expiration of the watchdog timer.
1
EEPROM fault
Enables IRQ to indicate a fault during an EEPROM upload or download operation.
0
EEPROM complete
Enables IRQ to indicate successful completion of an EEPROM upload or download operation.
Table 42. IRQ Mask for Reference Inputs
Address
Bits
Bit Name
Description
0x0110
7
Reserved
Reserved.
6
REFB validated
Enables IRQ to indicate that REFB has been validated.
5
REFB fault cleared
Enables IRQ to indicate that REFB has been cleared of a previous fault.
4
REFB fault
Enables IRQ to indicate that REFB has been faulted.
3
Reserved
Reserved.
2
REFA validated
Enables IRQ to indicate that REFA has been validated.
1
REFA fault cleared
Enables IRQ to indicate that REFA has been cleared of a previous fault.
0
REFA fault
Enables IRQ to indicate that REFA has been faulted.
0x0111
7
Reserved
Reserved.
6
REFD validated
Enables IRQ to indicate that REFD has been validated.
5
REFD fault cleared
Enables IRQ to indicate that REFD has been cleared of a previous fault.
4
REFD fault
Enables IRQ to indicate that REFD has been faulted.
3
Reserved
Reserved.
2
REFC validated
Enables IRQ to indicate that REFC has been validated.
1
REFC fault cleared
Enables IRQ to indicate that REFC has been cleared of a previous fault.
0
REFC fault
Enables IRQ to indicate that REFC has been faulted.



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