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Data Sheet

AD9554

Rev. D | Page 87 of 116

Table 92. DPLL_0 REFD Integer Part of Feedback (N0) Divider

Address

Bits

Bit Name

Description

0x046B

[7:0]

Digital PLL_0 feedback divider—Integer Part N0

Digital PLL_0 integer feedback divider (minus 1), Bits[7:0]. Default: 0x00.

0x046C

[7:0]

Digital PLL_0 integer feedback divider, Bits[15:8]. Default: 0x00.

0x046D

[7:2]

Reserved

Default: 0x00.

[1:0]

Digital PLL_0 feedback divider—Integer Part N0

Digital PLL_0 integer feedback divider, Bits[17:16]. Default: 00b.

Table 93. DPLL_0 REFD Fractional Part of Fractional Feedback Divider—FRAC0

Address

Bits

Bit Name

Description

0x046E

[7:0]

Digital PLL_0 fractional

feedback divider—FRAC0

The numerator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00.

0x046F

[7:0]

The numerator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00.

0x0470

[7:0]

The numerator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00.

Table 94. DPLL_0 REFD Modulus of Fractional Feedback Divider—MOD0

Address

Bits

Bit Name

Description

0x0471

[7:0]

Digital PLL_0 feedback

divider modulus—MOD0

The denominator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00.

0x0472

[7:0]

The denominator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00.

0x0473

[7:0]

The denominator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00.

DPLL_1 CONTROLS (REGISTER 0x0500 TO REGISTER 0x051E)

These registers mimic the DPLL_0 general settings registers (Register 0x0400 through Register 0x041E) but the register addresses are

offset by 0x0100. All default values are identical.

APLL_1 CONFIGURATION (REGISTER 0x0530 TO REGISTER 0x0533)

These registers mimic the APLL_0 configuration registers (Register 0x0430 through Register 0x0433) but the register addresses are offset

by 0x0100. All default values are identical.

PLL_1 OUTPUT SYNC AND CLOCK DISTRIBUTION (REGISTER 0x0534 TO REGISTER 0x053E)

These registers mimic the PLL_0 output SYNC and clock distribution registers (Register 0x0434 through Register 0x043E) but the register

addresses are offset by 0x0100. All default values are identical.

DPLL_1 SETTINGS FOR REFERENCE INPUT A (REFA) (REGISTER 0x0540 TO REGISTER 0x054C)

These registers mimic the DPLL_0 settings for the Reference Input A (REFA) registers (Register 0x0440 through Register 0x044C) but the

DPLL_1 SETTINGS FOR REFERENCE INPUT B (REFB) (REGISTER 0x054D TO REGISTER 0x0559)

These registers mimic the DPLL_0 settings for the Reference Input B (REFB) registers (Register 0x044D through Register 0x0459) but the

DPLL_1 SETTINGS FOR REFERENCE INPUT C (REFC) (REGISTER 0x055A TO REGISTER 0x0566)

These registers mimic the DPLL_0 settings for the Reference Input C (REFC) registers (Register 0x045A through Register 0x0466) but the

DPLL_1 SETTINGS FOR REFERENCE INPUT D (REFD) (REGISTER 0x0567 TO REGISTER 0x0573)

These registers mimic the DPLL_0 settings for the Reference Input D (REFD) registers (Register 0x0467 through Register 0x0473) but the

DPLL_2 CONTROLS (REGISTER 0x0600 TO REGISTER 0x061E)

These registers mimic the DPLL_0 controls registers (Register 0x0400 through Register 0x041E) but the register addresses are offset by

0x0200. All default values are identical.

APLL_2 CONFIGURATION (REGISTER 0x0630 TO REGISTER 0x0633)

These registers mimic the APLL_0 configuration registers (Register 0x0430 through Register 0x0433) but the register addresses are offset

by 0x0200. All default values are identical.

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