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AD9554 Datasheet(PDF) 65 Page - Analog Devices |
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AD9554 Datasheet(HTML) 65 Page - Analog Devices |
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65 / 116 page  Data Sheet AD9554 Rev. D | Page 65 of 116 Reg Addr (Hex) Option Name D7 D6 D5 D4 D3 D2 D1 D0 Def (Hex) Global Demapping Control 0x0900 L Demap control IO_UPDATE Reserved Demap control IO_ UPDATE 0x00 0x0901 DPLL_0 DPLL_0 sampled address, Bits[7:0] 0x00 0x0902 DPLL_0 sampled address, Bits[15:8] 0x00 0x0903 DPLL_1 DPLL_1 sampled address, Bits[7:0] 0x00 0x0904 DPLL_1 sampled address, Bits[15:8] 0x00 0x0905 DPLL_2 DPLL_2 sampled address, Bits[7:0] 0x00 0x0906 DPLL_2 sampled address, Bits[15:8] 0x00 0x0907 DPLL_3 DPLL_3 sampled address, Bits[7:0] 0x00 0x0908 DPLL_3 sampled address, Bits[15:8] 0x00 0x0909 Demap control IO_UPDATE Reserved Demap control IO_ UPDATE 0x00 Common Operational Controls 0x0A00 Global Reserved Soft sync all Calibrate SYSCLK Calibrate all Power- down all 0x00 0x0A01 Reference inputs Reserved REFD power- down REFC power- down REFB power- down REFA power- down 0x00 0x0A02 A Reserved REFD timeout REFC timeout REFB timeout REFA timeout 0x00 0x0A03 Reserved REFD fault REFC fault REFB fault REFA fault 0x00 0x0A04 Reserved REFD monitor bypass REFC monitor bypass REFB monitor bypass REFA monitor bypass 0x00 0x0A05 A Clear IRQ groups Clear watchdog timer Reserved Clear DPLL_3 IRQs Clear DPLL_2 IRQs Clear DPLL_1 IRQs Clear DPLL_0 IRQs Clear common IRQs Clear all IRQs 0x00 0x0A06 A Clear common IRQ SYSCLK unlocked SYSCLK stable SYSCLK locked SYSCLK cal ended SYSCLK cal started Watchdog timer EEPROM fault EEPROM complete 0x00 0x0A07 A Reserved REFB validated REFB fault cleared REFB fault Reserved REFA validated REFA fault cleared REFA fault 0x00 0x0A08 A Reserved REFD validated REFD fault cleared REFD fault Reserved REFC validated REFC fault cleared REFC fault 0x00 0x0A09 A Clear DPLL_0 IRQ Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked 0x00 0x0A0A A DPLL_0 switching DPLL_0 free run DPLL_0 holdover History updated REFD activated REFC activated REFB activated REFA activated 0x00 0x0A0B A Phase step detected Demap control unclamped Demap control clamped Clock dist sync’d APLL_0 unlocked APLL_0 locked APLL_0 cal ended APLL_0 cal started 0x00 0x0A0C A Clear DPLL_1 IRQ Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked 0x00 0x0A0D A DPLL_1 switching DPLL_1 free run DPLL_1 holdover History updated REFD activated REFC activated REFB activated REFA activated 0x00 0x0A0E A Phase step detected Demap control unclamped Demap control clamped Clock dist sync’d APLL_1 unlocked APLL_1 locked APLL_1 cal ended APLL_1 cal started 0x00 0x0A0F A Clear DPLL_2 IRQ Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked 0x00 0x0A10 A DPLL_2 switching DPLL_2 free run DPLL_2 holdover History updated REFD activated REFC activated REFB activated REFA activated 0x00 0x0A11 A Phase step detected Demap control unclamped Demap control clamped Clock dist sync’d APLL_2 unlocked APLL_2 locked APLL_2 cal ended APLL_2 cal started 0x00 0x0A12 A Clear DPLL_3 IRQ Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked 0x00 0x0A13 A DPLL_3 switching DPLL_3 free run DPLL_3 holdover History updated REFD activated REFC activated REFB activated REFA activated 0x00 0x0A14 A Phase step detected Demap control unclamped Demap control clamped Clock dist sync’d APLL_3 unlocked APLL_3 locked APLL_3 cal ended APLL_3 cal started 0x00 |
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