AD9554 datasheet(97/116 Pages) AD

97 / 116 page

Data Sheet

AD9554

Rev. D | Page 97 of 116

PLL_1 OPERATIONAL CONTROLS (REGISTER 0x0A40 TO REGISTER 0x0A44)

These registers mimic the PLL_0 controls registers (Register 0x0A20 through Register 0x0A24) but the register addresses are offset by

0x0020. All default values are identical.

PLL_2 OPERATIONAL CONTROLS (REGISTER 0x0A60 TO REGISTER 0x0A64)

These registers mimic the PLL_0 controls registers (Register 0x0A20 through Register 0x0A24) but the register addresses are offset by

0x0040. All default values are identical.

PLL_3 OPERATIONAL CONTROLS (REGISTER 0x0A80 TO REGISTER 0x0A84)

These registers mimic the PLL_0 controls registers (Register 0x0A20 through Register 0x0A24) but the register addresses are offset by

0x0060. All default values are identical.

VOLTAGE REGULATOR (REGISTER 0x0B00 TO REGISTER 0x0B01)

The bits in these registers adjust the internal voltage regulator for 1.5 V input voltage operation.

Table 115. Voltage Regulator

Address

Bits

Bit Name

Description

0x0B00

[7:0]

VREG, Bits[7:0]

Adjusts internal voltage regulators for 1.5 V operation. There are only two valid settings for this register, and

all bits in VREG[9:0] must be all 1s or all 0s, depending on whether the device is powered at 1.5 V or 1.8 V.

0x00 (default) = 1.8 V operation.

0xFF = 1.5 V operation.

0x0B01

[7:2]

Reserved

Default: 000000b.

[1:0]

VREG, Bits[9:8]

Adjusts internal voltage regulators for 1.5 V operation. There are only two valid settings for this register.

00b (default): 1.8 V operation.

11b: 1.5 V operation.

STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D05)

All bits in Register 0x0D00 to Register 0x0D05 are read only. To report the latest status, these bits require an IO_UPDATE

(Register 0x000F = 0x01) immediately before being read.

Table 116. EEPROM Status

Address

Bits

Bit Name

Description

0x0D00

[7:4]

Reserved

Default: 00000b.

EEPROM CRC fault detected

An CRC error occurred during an EEPROM operation.

EEPROM fault detected

An error occurred during an EEPROM operation.

EEPROM download in progress

The control logic sets this bit while data is being downloaded from the EEPROM.

EEPROM upload in progress

The control logic sets this bit while data is being uploaded to the EEPROM.

Table 117. SYSCLK and PLL Status

Address

Bits

Bit Name

Description

0x0D01

PLL_3 all locked

Indicates the status of the system clock, APLL_3, and DPLL_3.

0 = system clock or APLL_3 or DPLL_3 is unlocked.

1 = all three PLLs (system clock, APLL_3, and DPLL_3) are locked.

PLL_2 all locked

Indicates the status of the system clock, APLL_2, and DPLL_2.

0 = system clock or APLL_2 or DPLL_2 is unlocked.

1 = all three PLLs (system clock, APLL_2, and DPLL_2) are locked.

PLL_1 all locked

Indicates the status of the system clock, APLL_1, and DPLL_1.

0 = system clock or APLL_1 or DPLL_1 is unlocked.

1 = all three PLLs (system clock, APLL_1, and DPLL_1) are locked.

PLL_0 all locked

Indicates the status of the system clock, APLL_0, and DPLL_0.

0 = system clock or APLL_0 or DPLL_0 is unlocked.

1 = all three PLLs (system clock, APLL_0, and DPLL_0) are locked.

Reserved

Default: 0b.

AD9554 Datasheet(PDF) 97 Page - Analog Devices

AD9554 Datasheet(HTML) 97 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL