AD9554 datasheet(9/116 Pages) AD

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Data Sheet

AD9554

Rev. D | Page 9 of 116

DISTRIBUTION CLOCK OUTPUTS

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

14 mA (HCSL-, LVDS-COMPATIBLE) MODE

Unless otherwise stated, specifications dc-

coupled with no output termination resistor;

when ac-coupled, LVDS-compatible amplitudes are

achieved with a 100 Ω resistor across the output

pair; HCSL-compatible amplitudes achieved with

no termination resistor across the output pair;

output current setting: 14 mA

Output Frequency

0.430

941

MHz

Frequency range all four PLLs can generate using

unique VCO frequencies; frequencies outside this

range are possible on some of the PLLs, but can

result in increased VCO coupling due to multiple

PLLs using the same VCO frequency

Continuous Output Frequency Range

0.430

781

MHz

All four PLLs can generate this range at the same

time while using unique VCO frequencies

Maximum Output Frequency

PLL0 to PLL3 Using Unique VCO

Frequencies

941

MHz

Maximum frequency all four PLLs can generate

using unique VCO frequencies

PLL0, PLL1, and PLL2

1250

MHz

Limited by 1250 MHz maximum input frequency

to channel divider (Q divider)

PLL3

1187

MHz

Limited by 4748 MHz maximum VCO frequency

Rise/Fall Time (20% to 80%)1

125

190

Duty Cycle

Up to fOUT = 750 MHz

Up to fOUT = 941 MHz

Up to fOUT = 1250 MHz

Differential Output Voltage Swing

Differential voltage swing between output pins;

measured with output driver static; peak-to-peak

differential output amplitude 2× this level with

driver toggling; see Figure 11 for output

amplitude vs. output frequency

Without 100 Ω Termination Resistor

635

840

1000

With 100 Ω Termination Resistor Across

Outputs

294

390

463

Common-Mode Output Voltage

310

420

525

Output driver static; no termination resistor

Reference Input-to-Output Delay Variation

over Temperature

600

fs/°C

DPLL locked to same input reference at all times;

stable system clock source (noncrystal)

Static Phase Offset Variation from Active

Reference to Output over Voltage

Extremes

±75

fs/mV

21 mA MODE

Unless otherwise stated, specifications

dc-coupled with 50 Ω output termination resistor to

ground; output current setting = 21 mA

Output Frequency

0.430

941

MHz

Frequency range all four PLLs can generate using

unique VCO frequencies; frequencies outside this

range are possible on some of the PLLs, but can

result in increased VCO coupling due to multiple

PLLs using the same VCO frequency

Continuous Output Frequency Range

0.430

781

MHz

All four PLLs can generate this range at the same

time while using unique VCO frequencies

Maximum Output Frequency

PLL0 to PLL3 Using Unique VCO

Frequencies

941

MHz

Maximum frequency all four PLLs can generate

using unique VCO frequencies

PLL0, PLL1, and PLL2

1250

MHz

Limited by 1250 MHz maximum input frequency

to channel divider (Q divider)

PLL3

1187

MHz

Limited by 4748 MHz maximum VCO frequency

Rise/Fall Time (20% to 80%)1

125

190

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