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AD9554 Datasheet(PDF) 61 Page - Analog Devices |
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AD9554 Datasheet(HTML) 61 Page - Analog Devices |
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61 / 116 page  Data Sheet AD9554 Rev. D | Page 61 of 116 Reg Addr (Hex) Option Name D7 D6 D5 D4 D3 D2 D1 D0 Def (Hex) 0x040D DPLL_0 history mode Reserved Single sample fallback Persistent history Incremental average, Bits[2:0] 0x00 0x040E DPLL_0 closed loop phase offset (±0.5 ms) Fixed phase offset (signed; ps), Bits[7:0] 0x00 0x040F Fixed phase offset (signed; ps), Bits[15:8] 0x00 0x0410 Fixed phase offset (signed; ps), Bits[23:16] 0x00 0x0411 Reserved Fixed phase offset (signed; ps), Bits[29:24] 0x00 0x0412 Incremental phase offset step size (ps/step), Bits[7:0] (up to 65.5 ns/step) 0x00 0x0413 Incremental phase offset step size (ps/step), Bits[15:8] (up to 65.5 ns/step) 0x00 0x0414 DPLL_0 phase slew limit Phase slew rate limit (μs/sec), Bits[7:0] (315 μs/sec up to 65.536 ms/sec) 0x00 0x0415 Phase slew rate limit (μs/sec), Bits[15:8] (315 μs/sec up to 65.536 ms/sec) 0x00 0x0416 Demap enable Reserved Enable demap controller 0x00 0x0417 Demap sampled address Sampled address, Bits[7:0] 0x00 0x0418 Sampled address, Bits[15:8] 0x00 0x0419 Demap set point address Set point address, Bits[7:0] 0x00 0x041A Set point address, Bits[15:8] 0x00 0x041B Demap gain control Gain, Bits[7:0] 0x00 0x041C Gain, Bits[15:8] 0x00 0x041D Gain, Bits[23:16] 0x00 0x041E Demap clamp control Clamp value, Bits[7:0] 0x00 Output PLL_0 (APLL_0) and Channel 0 Output Drivers 0x0430 APLL_0 charge pump Reserved Output PLL0 (APLL_0) charge pump current, Bits[6:0] 0x2E 0x0431 APLL_0 M0 divider Output PLL0 (APLL_0) feedback (M0) divider, Bits[7:0] 0x00 0x0432 APLL_0 loop filter control APLL_0 loop filter control, Bits[7:0] 0x7F 0x0433 Reserved P0 divider reset APLL_0 loop filter control, Bit 8 0x00 0x0434 P0 divider Reserved P0 divider divide ratio, Bits[3:0] 0x00 0x0435 OUT0 sync Reserved Sync source selection Auto sync mode, Bits[1:0] 0x00 0x0436 Reserved APLL_0 mask sync Mask OUT0B sync Mask OUT0A sync 0x00 0x0437 OUT0A Reserved OUT0A mode Invert polarity 0x00 0x0438 Q0_A divider Q0_A divider, Bits[7:0] 0x00 0x0439 Reserved Q0_A divider, Bits[9:8] 0x00 0x043A Reserved Q0_A divider phase, Bits[5:0] 0x00 0x043B OUT0B Reserved OUT0B mode Invert polarity 0x08 0x043C Q0_B divider Q0_B divider, Bits[7:0] 0x00 0x043D Reserved Q0_B divider, Bits[9:8] 0x00 0x043E Reserved Q0_B divider phase, Bits[5:0] 0x00 DPLL_0 Settings for Reference Input A 0x0440 Reference priority Reserved REFA priority Enable REFA 0x00 0x0441 W2, L DPLL_0 loop BW (17 bits) Digital PLL_0 loop bandwidth scaling factor, Bits[7:0] (in units of 0.1 Hz) 0x00 0x0442 W2, L Digital PLL_0 loop bandwidth scaling factor, Bits[15:8] (in units of 0.1 Hz) 0x00 0x0443 W2, L Reserved Base loop filter selection Digital PLL_0 loop BW scaling factor, Bit 16 0x00 |
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