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AD9554 Datasheet(PDF) 62 Page - Analog Devices

Part # AD9554
Description  Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
PDF  116 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9554 Datasheet(HTML) 62 Page - Analog Devices

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AD9554
Data Sheet
Rev. D | Page 62 of 116
Reg
Addr
(Hex)
Option
Name
D7
D6
D5
D4
D3
D2
D1
D0
Def
(Hex)
0x0444
W2
DPLL_0
N0 divider
(18 bits)
Digital PLL_0 feedback divider—Integer Part N0, Bits[7:0]
0x00
0x0445
W2
Digital PLL_0 feedback divider—Integer Part N0, Bits[15:8]
0x00
0x0446
W2
Reserved
Digital PLL_0 feedback
divider, Integer Part N0,
Bits[17:16]
0x00
0x0447
W8
DPLL_0
fractional
feedback
divider
(24 bits)
Digital PLL_0 fractional feedback divider—FRAC0, Bits[7:0]
0x00
0x0448
W8
Digital PLL_0 fractional feedback divider—FRAC0, Bits[15:8]
0x00
0x0449
W8
Digital PLL_0 fractional feedback divider—FRAC0, Bits[23:16]
0x00
0x044A
W2
DPLL_0
fractional
feedback
divider
modulus
(24 bits)
Digital PLL_0 feedback divider modulus—MOD0, Bits[7:0]
0x00
0x044B
W2
Digital PLL_0 feedback divider modulus—MOD0, Bits[15:8]
0x00
0x044C
W2
Digital PLL_0 feedback divider modulus—MOD0, Bits[23:16]
0x00
DPLL_0 Settings for Reference Input B
0x044D
Reference
priority
Reserved
REFB priority
Enable REFB
0x00
0x044E
W2, L
DPLL_0
loop BW
(17 bits)
Digital PLL_0 loop bandwidth scaling factor, Bits[7:0] (unit: 0.1 Hz)
0x00
0x044F
W2, L
Digital PLL_0 loop bandwidth scaling factor, Bits[15:8] (unit: 0.1 Hz)
0x00
0x0450
W2, L
Reserved
Base loop
filter
selection
Digital
PLL_0 loop
BW scaling
factor,
Bit 16
0x00
0x0451
W2
DPLL_0
N0 divider
(18 bits)
Digital PLL_0 feedback divider—Integer Part N0, Bits[7:0]
0x00
0x0452
W2
Digital PLL_0 feedback divider—Integer Part N0, Bits[15:8]
0x00
0x0453
W2
Reserved
Digital PLL_0 feedback
divider—Integer Part N0,
Bits[17:16]
0x00
0x0454
W8
DPLL_0
fractional
feedback
divider
(24 bits)
Digital PLL_0 fractional feedback divider—FRAC0, Bits[7:0]
0x00
0x0455
W8
Digital PLL_0 fractional feedback divider—FRAC0, Bits[15:8]
0x00
0x0456
W8
Digital PLL_0 fractional feedback divider—FRAC0, Bits[23:16]
0x00
0x0457
W2
DPLL_0
fractional
feedback
divider
modulus
(24 bits)
Digital PLL_0 feedback divider modulus—MOD0, Bits[7:0]
0x00
0x0458
W2
Digital PLL_0 feedback divider modulus—MOD0, Bits[15:8]
0x00
0x0459
W2
Digital PLL_0 feedback divider modulus—MOD0, Bits[23:16]
0x00
DPLL_0 Settings for Reference Input C
0x045A
Reference
priority
Reserved
REFC priority
Enable REFC
0x00
0x045B
W2, L
DPLL_0
loop BW
(17 bits)
Digital PLL_0 loop bandwidth scaling factor, Bits[7:0] (unit: 0.1 Hz)
0x00
0x045C
W2, L
Digital PLL_0 loop bandwidth scaling factor, Bits[15:8] (unit: 0.1 Hz)
0x00
0x045D
W2, L
Reserved
Base loop
filter
selection
Digital
PLL_0 loop
BW scaling
factor,
Bit 16
0x00
0x045E
W2
DPLL_0
N0 divider
(18 bits)
Digital PLL_0 feedback divider—Integer Part N0, Bits[7:0]
0x00
0x045F
W2
Digital PLL_0 feedback divider—Integer Part N0, Bits[15:8]
0x00
0x0460
W2
Reserved
Digital PLL_0 feedback
divider—Integer Part N0,
Bits[17:16]
0x00
0x0461
W8
DPLL_0
fractional
feedback
divider
(24 bits)
Digital PLL_0 fractional feedback divider—FRAC0, Bits[7:0]
0x00
0x0462
W8
Digital PLL_0 fractional feedback divider—FRAC0, Bits[15:8]
0x00
0x0463
W8
Digital PLL_0 fractional feedback divider—FRAC0, Bits[23:16]
0x00
0x0464
W2
DPLL_0
fractional
feedback
divider
modulus
(24 bits)
Digital PLL_0 feedback divider modulus—MOD0, Bits[7:0]
0x00
0x0465
W2
Digital PLL_0 feedback divider modulus—MOD0, Bits[15:8]
0x00
0x0466
W2
Digital PLL_0 feedback divider modulus—MOD0, Bits[23:16]
0x00



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