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AD9554 Datasheet(PDF) 80 Page - Analog Devices

Part # AD9554
Description  Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
PDF  116 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9554 Datasheet(HTML) 80 Page - Analog Devices

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AD9554
Data Sheet
Rev. D | Page 80 of 116
Table 67. DPLL_0 Demapping Control
Address
Bits
Bit Name
Description
0x0416
[7:1]
Reserved
Reserved, Bits[7:1] (default: 0x00)
0
Enable demap controller
Enables the demapping controller.
0 (default) = The demapping controller is disabled.
1 = The demapping controller is enabled.
0x0417
[7:0]
Sampled address, Bits[15:0]
Sampled address, Bits[7:0]. Default: 0x00.
0x0418
[7:0]
Sampled address, Bits[15:8]. Default: 0x00.
0x0419
[7:0]
Set point address, Bits[15:0]
Set point address, Bits[7:0]. Default: 0x00.
0x041A
[7:0]
Set point address, Bits[15:8]. Default: 0x00.
0x041B
[7:0]
Gain, Bits[23:0]
Gain, Bits[7:0]. Default: 0x00.
0x041C
[7:0]
Gain, Bits[15:8]. Default: 0x00.
0x041D
[7:0]
Gain, Bits[23:16]. Default: 0x00.
0x041E
[7:0]
Clamp value, Bits[7:0]
Clamp value, Bits[7:0]. Default: 0x00.
APLL_0 CONFIGURATION (REGISTER 0x0430 TO REGISTER 0x0434)
Table 68. Output PLL_0 (APLL_0) Setting1
Address
Bits
Bit Name
Description
0x0430
7
Reserved
Default: 0b.
[6:0]
Output PLL0 (APLL_0) charge pump
current, Bits[6:0]
LSB: 3.5 μA. 0000001b = 1 × LSB; 0000010b = 2 × LSB; 1111111b = 127 × LSB.
Default: 0x2E = 451 μA CP current.
0x0431
[7:0]
Output PLL0 (APLL_0) feedback M0
divider, Bits[7:0]
Division: 14 to 255. Default: 0x00.
0x0432
[7:6]
APLL_0 loop filter control, Bits[7:0]
Second pole resistor (RP2). Default: 0x7F.
RP2 (Ω)
Bit 7
Bit 6
500
0
0
333 (default)
0
1
250
1
0
200
1
1
[5:3]
Zero resistor (RZERO).
RZERO (Ω)
Bit 5
Bit 4
Bit 3
1500
0
0
0
1250
0
0
1
1000
0
1
0
930
0
1
1
1250
1
0
0
1000
1
0
1
750
1
1
0
680 (default)
1
1
1
[2:0]
First pole capacitor (CP1).
CP1 (pF)
Bit 2
Bit 1
Bit 0
10
0
0
0
30
0
0
1
40
0
1
0
70
0
1
1
90
1
0
0
110
1
0
1
130
1
1
0
150 (default)
1
1
1



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