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AD9554 Datasheet(PDF) 67 Page - Analog Devices |
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AD9554 Datasheet(HTML) 67 Page - Analog Devices |
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67 / 116 page  Data Sheet AD9554 Rev. D | Page 67 of 116 Reg Addr (Hex) Option Name D7 D6 D5 D4 D3 D2 D1 D0 Def (Hex) 0x0D0E R, L IRQ, DPLL_1 Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked N/A 0x0D0F R, L DPLL_1 switching DPLL_1 free run DPLL_1 holdover DPLL_1 history updated REFD activated REFC activated REFB activated REFA activated N/A 0x0D10 R, L Phase step direction Demap control unclamped Demap control clamped Clock dist sync’d APLL_1 unlocked APLL_1 locked APLL_1 cal ended APLL_1 cal started N/A 0x0D11 R, L IRQ, DPLL_2 Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked N/A 0x0D12 R, L DPLL_2 switching DPLL_2 free run DPLL_2 holdover DPLL_2 history updated REFD activated REFC activated REFB activated REFA activated N/A 0x0D13 R, L Phase step direction Demap control unclamped Demap control clamped Clock dist sync’d APLL_2 unlocked APLL_2 locked APLL_2 cal ended APLL_2 cal started N/A 0x0D14 R, L IRQ, DPLL_3 Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked N/A 0x0D15 R, L DPLL_3 switching DPLL_3 free run DPLL_3 holdover DPLL_3 history updated REFD activated REFC activated REFB activated REFA activated N/A 0x0D16 R, L Phase step direction Demap control unclamped Demap control clamped Clock dist sync’d APLL_3 unlocked APLL_3 locked APLL_3 cal ended APLL_3 cal started N/A PLL_0 Read Only Status (To show the latest status, these registers require an IO_UPDATE before being read.) 0x0D20 R, L PLL_0 lock status Reserved APLL_0 cal in progress APLL_0 freq lock DPLL_0 freq lock DPLL_0 phase lock PLL_0 all locked N/A 0x0D21 R DPLL_0 loop state Reserved DPLL_0 active ref DPLL_0 switching DPLL_0 holdover DPLL_0 free run N/A 0x0D22 R Reserved Demap controller clamped DPLL_0 phase slew limited DPLL_0 frequency clamped DPLL_0 history available N/A 0x0D23 R DPLL_0 holdover history DPLL_0 tuning word readback, Bits[7:0] N/A 0x0D24 R DPLL_0 tuning word readback, Bits[15:8] N/A 0x0D25 R DPLL_0 tuning word readback, Bits[23:16] N/A 0x0D26 R Reserved DPLL_0 tuning word readback, Bits[29:24] N/A 0x0D27 R DPLL_0 phase lock detect bucket DPLL_0 phase lock detect bucket level, Bits[7:0] N/A 0x0D28 R Reserved DPLL_0 phase lock detect bucket level, Bits[11:8] N/A 0x0D29 R DPLL_0 frequency lock detect bucket DPLL_0 frequency lock detect bucket level, Bits[7:0] N/A 0x0D2A R Reserved DPLL_0 frequency lock detect bucket level, Bits[11:8] N/A PLL_1 Read Only Status (To show the latest status, these registers require an IO_UPDATE before being read.) 0x0D40 to 0x0D4A These registers mimic the PLL_0 read only status registers (0x0D20 through 0x0D2A) but the register addresses are offset by 0x0020. All default values are identical. N/A PLL_2 Read Only Status (To show the latest status, these registers require an IO_UPDATE before being read.) 0x0D60 to 0x0D6A These registers mimic the PLL_0 read only status registers (0x0D20 through 0x0D2A) but the register addresses are offset by 0x0040. All default values are identical. N/A PLL_3 Read Only Status (To show the latest status, these registers require an IO_UPDATE before being read.) 0x0D80 to 0x0D8A These registers mimic the PLL_0 Read Only Status registers (0x0D20 through 0x0D2A) but the register addresses are offset by 0x0060. All default values are identical. N/A Nonvolatile Memory (EEPROM) Control 0x0E00 E Write protect Reserved Enable I2C fast mode Write enable 0x00 0x0E01 E, L Condition Reserved Conditional value 0x00 0x0E02 L, A, E Save Reserved Save to EEPROM 0x00 0x0E03 L, A, E Load Reserved Load from EEPROM 0x00 |
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