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AD9554

Data Sheet

Rev. D | Page 30 of 116

This section provides a programming overview of the register

blocks in the AD9554, describing what they do and why they

are important. This is supplemental information only needed

when loading the registers without using the .STP file.

The AD9554 evaluation software contains a wizard that

determines the register settings based on the input and output

frequencies of the user. It is strongly recommended that the

evaluation software determine these settings.

Multifunction Pins (Optional)

To use any of the multifunction pins for status or control, this

step is required. The multifunction pin parameters are located

at Register 0x0100 to Register 0x010C.

Table 154 has a list of the Mx pin output functions, and Table 155

has a list of Mx pin input functions.

IRQ Functions (Optional)

To use the IRQ feature, this step is required. The IRQ functions

are divided into five groups: common, PLL_0, PLL_1, PLL_2,

and PLL_3.

First, choose the events that trigger an IRQ and then set them in

assigned to the IRQ function. The user can choose to dedicate

one Mx pin to each of the five IRQ groups, or one Mx pin can

be assigned for all IRQs.

The IRQ monitor registers are located at Register 0x0D08 to

IRQ monitor bit at Register 0x0D08 to Register 0x0D16 is set

high when the indicated event occurs.

Individual IRQ events are cleared by using the IRQ clearing

registers at Register 0x0A05 to Register 0x0A14 or by setting the

clear all IRQs bit (Register 0x0A05[0]) to 1b.

The default values of the IRQ mask registers are such that

interrupts are not generated. The default IRQ pin (and Mx pins)

mode is active high CMOS. The user can also select active low

CMOS, open-drain PMOS, and open-drain NMOS independently

on any of these pins.

Watchdog Timer (Optional)

To use the watchdog timer, this step is required. The watchdog

timer control is located at Register 0x010D and Register 0x010E.

The watchdog timer is disabled by default.

The watchdog timer is useful for generating an IRQ at a fixed

interval. The timer is reset by setting the clear watchdog timer

bit in Register 0x0A05[7] to 1.

The user can also program an Mx pin for the watchdog timer

output. In this mode, the Mx pin generates a 40 ns pulse every

time the watchdog timer expires.

System Clock Configuration

The system clock multiplier (SYSCLK) parameters are at

use the following steps:

Set the system clock PLL input type and divider values.

Set the system clock period. It is essential to program the

system clock period because many of the AD9554

subsystems rely on this value.

Set the system clock stability timer. The system clock stability

timer specifies the amount of time that the system clock PLL

must be locked before the device declares that the system

clock is stable. It is critical that the system clock stability timer

be set long enough to ensure that the external source is

completely stable when the timer expires. For instance, a

temperature compensated crystal oscillator (TCXO) can take

longer than 50 ms (the default value for the stability timer)

to stabilize after power is applied.

Update all registers (Register 0x000F = 0x01).

To calibrate the system clock on the next IO_UPDATE,

write Register 0x0A00 = 0x04.

Update all registers (Register 0x000F = 0x01).

Important Notes

If Bit 2 in Register 0x0A00 is set independently to initiate a

system clock PLL calibration, leave this bit set to 1 in all

subsequent writes to Register 0x0A00. If this bit is accidentally

cleared, recalibrate the system clock VCO or issue a calibrate all

command by setting Bit 1 in Register 0x0A00 and by issuing an

IO_UPDATE (Register 0x000F = 0x01).

In addition, the system clock PLL must be locked for the digital

PLL blocks to function correctly and to read back the registers

updated on the system clock domain. These registers include

the status registers, as well as the free running tuning word.

APLL calibration and input reference monitoring and validation

require that the system clock be stable. Therefore, first ensure

that the system clock is stable by checking Bit 1 in Register

0x0D01 when debugging the AD9554.

Reference Inputs

The reference input parameters and reference dividers are common

to all PLLs; there is only one reference divider (R divider) for each

reference input. The register address for each reference input follows:



These registers include the following settings:



Reference logic type (such as differential, single-ended)



Reference divider (20-bit R divider value)



Reference input period and tolerance



Reference validation timer



Phase and frequency lock detector settings



Phase step threshold

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