AD9554 datasheet(19/116 Pages) AD

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Data Sheet

AD9554

Rev. D | Page 19 of 116

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

LF_1

I/O

Loop filter for

APLL_1

Loop Filter Node for the APLL_1. Connect an external 15 nF capacitor from this

pin to Pin 33 (LDO_1).

LDO_1

LDO bypass

APLL_1 Loop Filter Voltage Regulator. Connect a 0.22 μF capacitor from this pin

to ground. This pin is also the ac ground reference for the integrated APLL_1

external loop filter.

OUT1B

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL1 Output 1B. This HCSL output can be configured as a LVDS- or LVPECL-

compatible output. LVPECL and LVDS levels can be achieved by ac-coupling

and using the Thevenin equivalent termination as described in the

Input/Output Termination Recommendations section.

OUT1B

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL1 Complementary Output 1B. Complementary signal to the output

provided on Pin 36 (OUT1B).

OUT1A

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL1 Output 1A. This HCSL output can be configured as a LVDS- or LVPECL-

compatible output. LVPECL and LVDS levels can be achieved by ac-coupling

and using the Thevenin equivalent termination as described in the

Input/Output Termination Recommendations section.

OUT1A

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL1 Complementary Output 1A. Complementary signal to the output

provided on Pin 39 (OUT1A).

REFB

Differential

input

Reference B Input. This internally biased input is typically ac-coupled; when

configured in this manner, it can accept any differential signal with single-

ended swing up to the VDD power supply. If dc-coupled, the input can be

LVDS or single-ended CMOS provided that VIH ≤ VDD.

REFB

Differential

input

Complementary Reference B Input. Complementary signal to the input

provided on Pin 43 (REFB). This pin can be left floating if REFB is a single-ended

input, or if REFB is not used.

REFC

Differential

input

Complementary Reference C Input. Complementary signal to the input

provided on Pin 48 (REFC). This pin can be left floating if REFC is a single-ended

input, or if REFC is not used.

REFC

Differential

input

Reference C Input. This internally biased input is typically ac-coupled; when

configured in this manner, it can accept any differential signal with single-

ended swing up to the VDD power supply. If dc-coupled, the input can be

LVDS or single-ended CMOS provided that VIH ≤ VDD.

OUT2A

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL2 Complementary Output 2A. Complementary signal to the output

provided on Pin 52 (OUT2A).

OUT2A

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL2 Output 2A. This HCSL output can be configured as a LVDS- or LVPECL-

compatible output. LVPECL and LVDS levels can be achieved by ac-coupling

and using the Thevenin equivalent termination as described in the

Input/Output Termination Recommendations section.

OUT2B

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL2 Complementary Output 2B. Complementary signal to the output

provided on Pin 55 (OUT2B).

OUT2B

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL2 Output 2B. This HCSL output can be configured as a LVDS- or LVPECL-

compatible output. LVPECL and LVDS levels can be achieved by ac-coupling

and using the Thevenin equivalent termination as described in the

Input/Output Termination Recommendations section.

LDO_2

LDO bypass

APLL_2 Loop Filter Voltage Regulator. Connect a 0.22 μF capacitor from this pin

to ground. This pin is also the ac ground reference for the integrated APLL_2

external loop filter.

LF_2

I/O

Loop filter for

APLL_2

Loop Filter Node for the APLL_2. Connect an external 15 nF capacitor from this

pin to Pin 58 (LDO_2).

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