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Data Sheet

AD9554

Rev. D | Page 85 of 116

Table 82. DPLL_0 REFB Integer Part of Feedback (N0) Divider

Address

Bits

Bit Name

Description

0x0451

[7:0]

Digital PLL_0 feedback divider—Integer Part N0

Digital PLL_0 integer feedback divider (minus 1), Bits[7:0]. Default: 0x00.

0x0452

[7:0]

Digital PLL_0 integer feedback divider, Bits[15:8]. Default: 0x00.

0x0453

[7:2]

Reserved

Default: 0x00.

[1:0]

Digital PLL_0 feedback divider—Integer Part N0

Digital PLL_0 integer feedback divider, Bits[17:16]. Default: 00.

Table 83. DPLL_0 REFB Fractional Part of Fractional Feedback Divider—FRAC0

Address

Bits

Bit Name

Description

0x0454

[7:0]

Digital PLL_0 fractional

feedback divider—FRAC0

The numerator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00.

0x0455

[7:0]

The numerator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00.

0x0456

[7:0]

The numerator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00.

Table 84. DPLL_0 REFB Modulus of Fractional Feedback Divider—MOD0

Address

Bits

Bit Name

Description

0x0457

[7:0]

Digital PLL_0 feedback

divider modulus—MOD0

The denominator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00.

0x0458

[7:0]

The denominator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00.

0x0459

[7:0]

The denominator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00.

DPLL_0 SETTINGS FOR REFERENCE INPUT C (REFC) (REGISTER 0x045A TO REGISTER 0x0466)

Table 85. DPLL_0 REFC Priority Setting

Address

Bits

Bit Name

Description

0x045A

[7:3]

Reserved

Default: 00000b.

[2:1]

REFC priority

These bits set the priority level (0 to 3) of REFC relative to the other input references.

00 (default) = 0 (highest).

01 = 1.

10 = 2.

11 = 3.

Enable REFC

This bit enables DPLL_0 to lock to REFC.

0 (default) = REFC is not enabled for use by DPLL_0.

1 = REFC is enabled for use by DPLL_0.

Table 86. DPLL_0 REFC Loop Bandwidth Scaling Factor

Address

Bits

Bit Name

Description

0x045B

[7:0]

Digital PLL_0 loop

bandwidth scaling factor

(unit of 0.1 Hz)

Digital PLL_0 loop bandwidth scaling factor, Bits[7:0]. Default: 0x00.

0x045C

[7:0]

Digital PLL_0 loop bandwidth scaling factor, Bits[15:8]. Default: 0x00. The default for

less than the DPLL phase detector frequency divided by 20. The DPLL may not lock

reliably if the DPLL loop bandwidth is <50 Hz and a crystal is used for the system clock.

See the Choosing the SYSCLK Source section for details.

0x045D

[7:2]

Reserved

Default: 0x00.

Base loop filter selection

0 = base loop filter with normal (70°) phase margin (default).

1 = base loop filter with high phase margin. For loop bandwidth ≤2 kHz, there is ≤0.1 dB

peaking in the closed-loop transfer function. Setting this bit is also recommended for

loop bandwidths >2 kHz.)

Digital PLL_0 loop BW

scaling factor (unit of 0.1 Hz)

Digital PLL_0 loop bandwidth scaling factor, Bit 16 (default: 0b).

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