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AD9554 Datasheet(PDF) 40 Page - Analog Devices |
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AD9554 Datasheet(HTML) 40 Page - Analog Devices |
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40 / 116 page  AD9554 Data Sheet Rev. D | Page 40 of 116 System Clock Stability Timer Because multiple blocks inside the AD9554 depend on the system clock being at a known frequency, the system clock must be stable before activating the monitors. At initial power-up, the system clock status is not known; therefore, it is reported as being unstable. After the system clock registers have been programmed and the SYSCLK VCO has been calibrated, the system clock PLL locks shortly thereafter. When the SYSCLK PLL locks, a timer runs for the duration stored in the system clock stability period registers. If the locked condition is violated any time during this waiting period, the timer is reset and halted until a locked condition is reestablished. After the specified period elapses, the internal logic of the AD9554 reports the system clock as stable. Note that any time the system clock stability timer is changed in Register 0x0206 through Register 0x0208, it is reset automatically. The system clock stability timer starts counting when the next IO_UDATE is issued (assuming that the system clock PLL is locked). |
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