AD9554 datasheet(6/116 Pages) AD

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AD9554

Data Sheet

Rev. D | Page 6 of 116

POWER DISSIPATION

Typical (typ) values apply for VDD = 1.8 V and maximum (max) values for VDD = 1.89 V.

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER DISSIPATION

Typical Configuration

0.94

1.1

System clock: 49.152 MHz crystal; four DPLLs active;

two 19.44 MHz input references in differential mode;

four ac-coupled output drivers in 21 mA mode at

644.53125 MHz

All Blocks Running

1.3

1.47

System clock: 49.152 MHz crystal; four DPLLs active, four

19.44 MHz input references in differential mode; eight

ac-coupled output drivers in 28 mA mode at 750 MHz

Full Power-Down

174

Measured using the Typical Configuration parameter

(see Table 3) and then setting the full power down bit

Incremental Power Dissipation

Typical configuration; table values show the change in

power due to the indicated operation

Complete DPLL/APLL On/Off

190

Power delta computed relative to the typical configuration;

the blocks powered down include one reference input,

one DPLL, one APLL, one P divider, two channel dividers,

and one output driver in 21 mA mode

Input Reference On/Off

Differential (Normal Mode)

22.5

fREF = 19.44 MHz

Differential (DC-Coupled LVDS)

24.6

fREF = 19.44 MHz

Single-Ended

14.3

fREF = 19.44 MHz

Output Distribution Driver On/Off

28 mA Mode (at 644.53 MHz)

21 mA Mode (at 644.53 MHz)

14 mA mode (at 644.53 MHz)

23.6

SYSTEM CLOCK INPUTS (XOA, XOB)

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SYSTEM CLOCK MULTIPLIER

PLL Output Frequency Range

2250

2415

MHz

Voltage controlled oscillator (VCO) range can place

limitations on nonstandard system clock input frequencies

Phase Frequency Detector (PFD) Rate

300

MHz

Frequency Multiplication Range

241

Assumes valid system clock and PFD rates

SYSTEM CLOCK REFERENCE INPUT PATH

System clock input must be ac-coupled

Input Frequency Range

System Clock Input Doubler Disabled

268

MHz

System Clock Input Doubler Enabled

150

MHz

Minimum Input Slew Rate

250

V/μs

Minimum limit imposed for jitter performance

Self-Biased Common-Mode Voltage

0.72

Internally generated

Input High Voltage

0.9

For ac-coupled single-ended operation

Input Low Voltage

0.5

For ac-coupled single-ended operation

Differential Input Voltage Sensitivity

250

mV p-p

Minimum voltage across pins required to ensure

switching between logic states; the instantaneous voltage

on either pin must not exceed 1.14 V; single-ended input

can be accommodated by ac grounding complementary

input; 800 mV p-p recommended for optimal jitter

performance

System Clock Input Doubler Duty Cycle

Amount of duty-cycle variation that can be tolerated on

the system clock input to use the doubler

System Clock Input = 20 MHz to 150 MHz

System Clock Input = 16 MHz to 20 MHz

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