AD9554 datasheet(90/116 Pages) AD

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AD9554

Data Sheet

Rev. D | Page 90 of 116

Table 97. Global Demapping Control

Address

Bits

Bit Name

Description

0x0900

[7:1]

Reserved

Reserved, Bits[7:1]. Default = 0x00.

Demap control IO_UPDATE

Demap control IO_UPDATE, Bit 0. Default = 0b.

0x0901

[7:0]

DPLL_0 sampled address, Bits[15:0]

DPLL_0 sampled address, Bits[7:0]. Default = 0x00.

0x0902

[7:0]

DPLL_0 sampled address, Bits[15:8]. Default: 0x00.

0x0903

[7:0]

DPLL_1 sampled address, Bits[15:0]

DPLL_1 sampled address, Bits[7:0]. Default = 0x00.

0x0904

[7:0]

DPLL_1 sampled address, Bits[15:8]. Default: 0x00.

0x0905

[7:0]

DPLL_2 sampled address, Bits[15:0]

DPLL_2 sampled address, Bits[7:0]. Default = 0x00.

0x0906

[7:0]

DPLL_2 sampled address, Bits[15:8]. Default: 0x00

0x0907

[7:0]

DPLL_3 sampled address, Bits[15:0]

DPLL_3 sampled address, Bits[7:0]. Default = 0x00.

0x0908

[7:0]

DPLL_3 sampled address, Bits[15:8]. Default: 0x00.

0x0909

[7:1]

Reserved

Reserved, Bits[7:1]. Default = 0x00.

Demap control IO_UPDATE

Demap control IO_UPDATE, Bit 0. Default = 0b.

COMMON OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A0E)

Table 98. Global Operational Controls

Address

Bits

Bit Name

Description

0x0A00

[7:4]

Reserved

Default: 0x0.

Soft sync all

Setting this bit initiates synchronization of all clock distribution outputs (default = 0b).

Nonmasked outputs stall when value is 1; restart is initialized on a 1-to-0 transition. Note

that like all buffered registers, an IO_UPDATE (0x000F = 0x01) is needed every time there is

a change for this bit to take effect.

Calibrate SYSCLK

A 0-to-1 transition of this bit (followed by an IO_UPDATE) calibrates the SYSCLK PLL.

Default: 0b.

Calibrate all

A 0-to-1 transition of this bit (followed by an IO_UPDATE) calibrates the system clock PLL, as

well as all four output PLLs (APLL_0, APLL_1, APLL_2, APLL_3). Default: 0b. Note that like all

buffered registers, an IO_UPDATE (0x000F = 0x01) is needed every time there is a change

for this bit to take effect. This bit is not self clearing; however, it is strongly recommended to

clear this bit after using it. If this bit is set, calibration of the individual APLLs (APLL_0,

APLL_1, APLL_2, and APLL_3) in Register 0xA20, Register 0xA40, Register 0xA60, and

Power-down all

Places the entire device in deep sleep mode. Default: device is not powered down.

Table 99. Power Down of Reference Inputs

Address

Bits

Bit Name

Description

0x0A01

[7:4]

Reserved

Default: 0x0

REFD power-down

Powers down REFD input receiver

0 (default) = not powered down

1 = powered down

REFC power-down

Powers down REFC input receiver

0 (default) = not powered down

1 = powered down

REFB power-down

Powers down REFB input receiver

0 (default) = not powered down

1 = powered down

REFA power-down

Powers down REFA input receiver

0 (default) = not powered down

1 = powered down

AD9554 Datasheet(PDF) 90 Page - Analog Devices

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