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Data Sheet

AD9554

Rev. D | Page 41 of 116

OUTPUT ANALOG PLL (APLL)

There are four output analog PLLs (APLLs) on the AD9554.

They provide the frequency upconversion from the digital PLL

(DPLL) outputs. The frequency ranges for each APLL are in

Table 11.

Each APLL also provides a noise filter on the DPLL output. The

APLL reference input is the output of the DPLL. The feedback

divider is an integer divider. The loop filter is partially integrated

with one external 15 nF capacitor that connects to the internal

LDO. In addition to the capacitor, there is an additional 0.22 μF

capacitor from the LDO pin to ground. The nominal loop

bandwidth for all four APLLs is 240 kHz.

The APLL_0 block diagram is shown in Figure 34. APLL_1

through APLL_3 are copies of APLL_0 with different VCO

ranges. Each APLL_x input is connected to the respective

DPLL_x output, and each APLL_x output is connected to the

respective Px divider.

LF_0 CAP

LF_0 PIN

VCO_0

PFD

FROM DPLL_0

TO P0

DIVIDER

INTEGER DIVIDER

OUTPUT PLL (APLL_0)

÷M0

LDO_0 PIN 22

Figure 34. APLL_0 Block Diagram

APLL CONFIGURATION

The frequency wizard that is included in the evaluation software

configures the APLL, and the user must not need to make

changes to the APLL settings. However, there may be special

cases where the user may want to adjust the APLL loop band-

width to meet a specific phase noise requirement. The easiest

way to change the APLL loop bandwidth is to adjust the APLL

charge pump current, which is controlled in the following

registers:



There is sufficient stability (68° of phase margin) in the APLL

default settings to permit a broad range of adjustment without

causing the APLL to be unstable.

APLL CALIBRATION

Calibration of the APLLs must be performed at startup and

whenever the nominal input frequency to the APLL changes by

more than ±100 ppm; although, the APLL maintains lock over

voltage and temperature extremes without recalibration.

APLL calibration at startup is normally performed during initial

Programming Using a Register Setup File section.

To recalibrate the APLL VCO after the chip has been running,

first, input the new settings (if any). The user can calibrate

APLL_0 without disturbing any of the other three APLLs

(APLL_1, APLL_2, and APLL_3).

Use the following steps to recalibrate the APLL VCO. It is

important to note that an IO_UPDATE (Register 0x000F =

0x01) is needed after each of these steps.

Ensure that the DPLL free run tuning word is set

(Register 0x0A22[0] = 1b for DPLL_0,

Clear the desired APLL calibration bit

(Register 0x0A20[1] = 0b for APLL_0,

Alternatively, the user can write Register 0xA00 = 0x00 to

clear the calibrate all bit. This allows the user to set this bit

in the next step to calibrate all four VCOs at the same time.

Set the desired APLL calibration bit

(Register 0x0A20[1] = 1b for APLL_0,

Alternatively, the user can write Register 0xA00 = 0x02 to

calibrate all four VCOs at the same time.

To ensure that the APLLs have locked, poll the APLL lock

status (Register 0x0D20[3] = 1b indicates lock for APLL_0,

Ensure that the DPLL free run tuning word is cleared

(Register 0x0A22[0] = 0b for DPLL_0,

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