AD9554 datasheet(95/116 Pages) AD

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Data Sheet

AD9554

Rev. D | Page 95 of 116

Table 109. IRQ Clearing for Digital PLL3 (DPLL_3)

Address

Bits

Bit Name

Description

0x0A12

Frequency unclamped

Clears IRQ indicating that DPLL_3 has exited a frequency unclamped state

Frequency clamped

Clears IRQ indicating that DPLL_3 has entered a frequency clamped state

Phase slew unlimited

Clears IRQ indicating that DPLL_3 has exited a phase slew limited state

Phase slew limited

Clears IRQ indicating that DPLL_3 has entered a phase slew limited state

Frequency unlocked

Clears IRQ indicating that DPLL_3 has lost frequency lock

Frequency locked

Clears IRQ indicating that DPLL_3 has acquired frequency lock

Phase unlocked

Clears IRQ indicating that DPLL_3 has lost phase lock

Phase locked

Clears IRQ indicating that DPLL_3 has acquired phase lock

0x0A13

DPLL_3 switching

Clears IRQ indicating that DPLL_3 is switching to a new reference

DPLL_3 free run

Clears IRQ indicating that DPLL_3 has entered free run mode

DPLL_3 holdover

Clears IRQ indicating that DPLL_3 has entered holdover mode

History updated

Clears IRQ indicating that DPLL_3 has updated its tuning word history

REFD activated

Clears IRQ indicating that DPLL_3 has activated REFD

REFC activated

Clears IRQ indicating that DPLL_3 has activated REFC

REFB activated

Clears IRQ indicating that DPLL_3 has activated REFB

REFA activated

Clears IRQ indicating that DPLL_3 has activated REFA

0x0A14

Phase step detected

Clears IRQ indicating that DPLL_3 has detected a large phase step at its input

Demap control unclamped

Clears IRQ indicating that the DPLL_3 demapping controller is unclamped

Demap control clamped

Clears IRQ indicating that the DPLL_3 demapping controller is clamped

Clock dist sync’d

Clears IRQ indicating a distribution sync event

APLL_3 unlocked

Clears IRQ indicating that APLL_3 has been unlocked

APLL_3 locked

Clears IRQ indicating that APLL_3 has been locked

APLL_3 cal ended

Clears IRQ indicating that APLL_3 calibration complete

APLL_3 cal started

Clears IRQ indicating that APLL_3 calibration started

PLL_0 OPERATIONAL CONTROLS (REGISTER 0x0A20 TO REGISTER 0x0A24)

Table 110. PLL_0 Sync and Calibration

Address

Bits

Bit Name

Description

0x0A20

[7:3]

Reserved

Default: 0x0.

APLL_0 soft sync

Setting this bit initiates synchronization of the clock distribution output.

0 (default) = normal operation.

1 = nonmasked PLL_0 outputs stall; restart initialized on a 1-to-0 transition.

APLL_0 calibrate (not self-

clearing)

1 = initiates VCO calibration (calibration occurs on the IO_UPDATE following a 0-to-1

transition of this bit.) This bit is not autoclearing.

0 (default) = does nothing.

PLL_0 power-down

Places DPLL_0, APLL_0, and PLL_0 clock in deep sleep mode.

0 (default) = normal operation.

1 = powered down.

Table 111. PLL_0 Output

Address

Bits

Bit Name

Description

0x0A21

[7:4]

Reserved

Default 0x0

OUT0B disable

Setting this bit puts the OUT0B driver into power-down. Default: 0b. Channel

synchronization is maintained, but runt pulses may be generated.

OUT0A disable

Setting this bit puts the OUT0A driver into power-down. Default: 0b. Channel

synchronization is maintained, but runt pulses may be generated.

OUT0B power-down

Setting this bit puts the OUT0B divider and driver into power-down. Default: 0b. This

mode saves the most power, but runt pulses may be generated during exit.

OUT0A power-down

Setting this bit puts the OUT0A divider and driver into power-down. Default: 0b. This

mode saves the most power, but runt pulses may be generated during exit.

AD9554 Datasheet(PDF) 95 Page - Analog Devices

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