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AD9554 Datasheet(PDF) 100 Page - Analog Devices |
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AD9554 Datasheet(HTML) 100 Page - Analog Devices |
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100 / 116 page  AD9554 Data Sheet Rev. D | Page 100 of 116 Address Bits Bit Name Description 0x0D0D 7 Phase step direction IRQ indicating that the DPLL_0 demapping controller phase step direction 6 Demap control unclamped IRQ indicating that the DPLL_0 demapping controller is unclamped 5 Demap control clamped IRQ indicating that the DPLL_0 demapping controller is clamped 4 Clock dist sync’d IRQ indicating a distribution sync event 3 APLL_0 unlocked IRQ indicating that APLL_0 has been unlocked 2 APLL_0 locked IRQ indicating that APLL_0 has been locked 1 APLL_0 cal ended IRQ indicating that APLL_0 calibration complete 0 APLL_0 cal started IRQ indicating that APLL_0 calibration started Table 121. IRQ Monitor for Digital PLL1 (DPLL_1) Address Bits Bit Name Description 0x0D0E 7 Frequency unclamped IRQ indicating that DPLL_1 has exited a frequency clamped state 6 Frequency clamped IRQ indicating that DPLL_1 has entered a frequency clamped state 5 Phase slew unlimited IRQ indicating that DPLL_1 has exited a phase slew limited state 4 Phase slew limited IRQ indicating that DPLL_1 has entered a phase slew limited state 3 Frequency unlocked IRQ indicating that DPLL_1 has lost frequency lock 2 Frequency locked IRQ indicating that DPLL_1 has acquired frequency lock 1 Phase unlocked IRQ indicating that DPLL_1 has lost phase lock 0 Phase locked IRQ indicating that DPLL_1 has acquired phase lock 0x0D0F 7 DPLL_1 switching IRQ indicating that DPLL_1 is switching to a new reference 6 DPLL_1 free run IRQ indicating that DPLL_1 has entered free run mode 5 DPLL_1 holdover IRQ indicating that DPLL_1 has entered holdover mode 4 DPLL_1 history updated IRQ indicating that DPLL_1 has updated its tuning word history 3 REFD activated IRQ indicating that DPLL_1 has activated REFD 2 REFC activated IRQ indicating that DPLL_1 has activated REFC 1 REFB activated IRQ indicating that DPLL_1 has activated REFB 0 REFA activated IRQ indicating that DPLL_1 has activated REFA 0x0D10 7 Phase step direction IRQ indicating that the DPLL_1 demapping controller phase step direction 6 Demap control unclamped IRQ indicating that the DPLL_1 demapping controller is unclamped 5 Demap control clamped IRQ indicating that the DPLL_1 demapping controller is clamped 4 Clock dist sync’d IRQ indicating a distribution sync event 3 APLL_1 unlocked IRQ indicating that APLL_1 has been unlocked 2 APLL_1 locked IRQ indicating that APLL_1 has been locked 1 APLL_1 cal ended IRQ indicating that APLL_1 calibration complete 0 APLL_1 cal started IRQ indicating that APLL_1 calibration started |
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