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AD9554 Datasheet(PDF) 103 Page - Analog Devices |
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AD9554 Datasheet(HTML) 103 Page - Analog Devices |
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103 / 116 page  Data Sheet AD9554 Rev. D | Page 103 of 116 Table 125. DPLL_0 Loop State Address Bits Bit Name Description 0x0D21 [7:5] Reserved Default: 000b. [4:3] DPLL_0 active ref Indicates the reference input that DPLL_0 is using. 00 = DPLL_0 has selected REFA. 01 = DPLL_0 has selected REFB. 10 = DPLL_0 has selected REFC. 11 = DPLL_0 has selected REFD. 2 DPLL_0 switching Indicates that DPLL_0 is switching input references. 0 = DPLL is not switching. 1 = DPLL is switching input references. 1 DPLL_0 holdover Indicates that DPLL_0 is in holdover mode. 0 = not in holdover. 1 = in holdover mode. 0 DPLL_0 free run Indicates that DPLL_0 is in free run mode. 0 = not in free run mode. 1 = in free run mode. 0x0D22 [7:4] Reserved Default: 00000b. 3 Demap controller clamped The control logic sets this bit when DPLL_0 demapping controller is clamped. 2 DPLL_0 phase slew limited The control logic sets this bit when DPLL_0 is phase slew limited. 1 DPLL_0 frequency clamped The control logic sets this bit when DPLL_0 is frequency clamped. 0 DPLL_0 history available The control logic sets this bit when the tuning word history of DPLL_0 is available. (See Register 0x0D23 to Register 0x0D26 for the tuning word.) Table 126. DPLL_0 Holdover History Address Bits Bit Name Description 0x0D23 [7:0] DPLL_0 tuning word readback, Bits[23:0] DPLL_0 tuning word readback bits, Bits[7:0]. This group of registers contains the averaged digital PLL tuning word used when the DPLL enters holdover. Setting the history accumulation timer to its minimal value allows the user to use these registers for a read back of the most recent DPLL tuning word with only 1 ms of averaging. Instantaneous tuning word readback is not available. 0x0D24 [7:0] DPLL_0 tuning word readback, Bits[15:8]. 0x0D25 [7:0] DPLL_0 tuning word readback, Bits[23:16]. 0x0D26 [7:6] Reserved Reserved. [5:0] DPLL_0 tuning word readback, Bits[29:24] DPLL_0 tuning word readback, Bits[29:24]. Table 127. DPLL_0 Phase Lock and Frequency Lock Bucket Levels Address Bits Bit Name Description 0x0D27 [7:0] DPLL_0 phase lock detect bucket level Read only digital PLL lock detect bucket level, Bits[7:0]; see the DPLL Frequency Lock Detector section for details. 0x0D28 [7:4] Reserved Reserved. [3:0] DPLL_0 phase lock detect bucket level Read only digital PLL lock detect bucket level, Bits[11:8]; see the DPLL Frequency Lock Detector section for details. 0x0D29 [7:0] DPLL_0 frequency lock detect bucket level Read only digital PLL lock detect bucket level, Bits[7:0]; see the DPLL Phase Lock Detector section for details. 0x0D2A [7:4] Reserved Reserved. [3:0] DPLL_0 frequency lock detect bucket level Read only digital PLL lock detect bucket level, Bits[11:8]; see the DPLL Phase Lock Detector section for details. |
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