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AD9554 Datasheet(PDF) 104 Page - Analog Devices

Part # AD9554
Description  Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
PDF  116 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9554 Datasheet(HTML) 104 Page - Analog Devices

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AD9554
Data Sheet
Rev. D | Page 104 of 116
PLL_1 READ ONLY STATUS (REGISTER 0x0D40 TO REGISTER 0x0D4A)
These registers mimic the PLL_0 control registers (Register 0x0D20 through Register 0x0D2A) but the register addresses are offset by
0x0020. All default values are identical. All bits in Register 0x0D40 to Register 0x0D4A are read only. To report the latest status, these bits
require an IO_UPDATE (Register 0x000F = 0x01) immediately before being read.
PLL_2 READ ONLY STATUS (REGISTER 0x0D60 TO REGISTER 0x0D6A)
These registers mimic the PLL_0 control registers (Register 0x0D20 through Register 0x0D2A) but the register addresses are offset by
0x0040. All bits in Register 0x0D60 to Register 0x0D6A are read only. To report the latest status, these bits require an IO_UPDATE
(Register 0x000F = 0x01) immediately before being read.
PLL_3 READ ONLY STATUS (REGISTER 0x0D80 TO REGISTER 0x0D8A)
These registers mimic the PLL_0 control registers (Register 0x0D20 through Register 0x0D2A) but the register addresses are offset by
0x0060. All bits in Register 0x0D40 to Register 0x0D4A are read only. To report the latest status, these bits require an IO_UPDATE
(Register 0x000F = 0x01) immediately before being read.
EEPROM CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E03)
Table 128. Nonvolatile Memory (EEPROM) Control
Address
Bits
Bit Name
Description
0x0E00
[7:2]
Reserved
Reserved
1
Enable I2C fast mode
Sets the speed of the external I2C EEPROM interface.
0 (default) = 100 kHz.
1 = 400 kHz.
0
Write enable
EEPROM write enable.
0 (default) = EEPROM write disabled.
1 = EEPROM write enabled. Note that the external EEPROM may have its own write
protect mechanism that is not controlled by this bit.
0x0E01
[7:4]
Reserved
Reserved.
[3:0]
Conditional value
When set to a nonzero value, it establishes the condition for EEPROM downloads.
The default value is 0. A value of 0 indicates that the power-up/reset condition is
used. Any nonzero value overrides this condition.
0x0E02
[7:1]
Reserved
Reserved.
0
Save to EEPROM
Uploads data to the EEPROM (see the EEPROM Storage Sequence (Register 0x0E10
to Register 0x0E61) section for more information). This bit is autoclearing.
0x0E03
[7:1]
Reserved
Reserved.
0
Load from EPROM
Downloads data from the EEPROM. This bit is autoclearing.



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