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AD9554 Datasheet(PDF) 102 Page - Analog Devices |
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AD9554 Datasheet(HTML) 102 Page - Analog Devices |
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102 / 116 page  AD9554 Data Sheet Rev. D | Page 102 of 116 Table 123. IRQ Monitor for Digital PLL3 (DPLL_3) Address Bits Bit Name Description 0x0D14 7 Frequency unclamped IRQ indicating that DPLL_3 has exited a frequency clamped state 6 Frequency clamped IRQ indicating that DPLL_3 has entered a frequency clamped state 5 Phase slew unlimited IRQ indicating that DPLL_3 has exited a phase slew limited state 4 Phase slew limited IRQ indicating that DPLL_3 has entered a phase slew limited state 3 Frequency unlocked IRQ indicating that DPLL_3 has lost frequency lock 2 Frequency locked IRQ indicating that DPLL_3 has acquired frequency lock 1 Phase unlocked IRQ indicating that DPLL_3 has lost phase lock 0 Phase locked IRQ indicating that DPLL_3 has acquired phase lock 0x0D15 7 DPLL_3 switching IRQ indicating that DPLL_3 is switching to a new reference 6 DPLL_3 free run IRQ indicating that DPLL_3 has entered free run mode 5 DPLL_3 holdover IRQ indicating that DPLL_3 has entered holdover mode 4 DPLL_3 history updated IRQ indicating that DPLL_3 has updated its tuning word history 3 REFD activated IRQ indicating that DPLL_3 has activated REFD 2 REFC activated IRQ indicating that DPLL_3 has activated REFC 1 REFB activated IRQ indicating that DPLL_3 has activated REFB 0 REFA activated IRQ indicating that DPLL_3 has activated REFA 0x0D16 7 Phase step direction IRQ indicating that the DPLL_3 demapping controller phase step direction 6 Demap control unclamped IRQ indicating that the DPLL_3 demapping controller is unclamped 5 Demap control clamped IRQ indicating that the DPLL_3 demapping controller is clamped 4 Clock dist sync’d IRQ indicating a distribution sync event 3 APLL_3 unlocked IRQ indicating that APLL_3 has been unlocked 2 APLL_3 locked IRQ indicating that APLL_3 has been locked 1 APLL_3 cal ended IRQ indicating that APLL_3 calibration complete 0 APLL_3 cal started IRQ indicating that APLL_3 calibration started PLL_0 READ ONLY STATUS (REGISTER 0x0D20 TO REGISTER 0x0D2A) All bits in Register 0x0D20 to Register 0x0D2A are read only. To report the latest status, these bits require an IO_UPDATE (Register 0x000F = 0x01) immediately before being read. Table 124. PLL_0 Lock Status Address Bits Bit Name Description 0x0D20 [7:5] Reserved Default: 000b. 4 APLL_0 cal in progress The control logic holds this bit set while the calibration of the APLL_0 VCO is in progress. 3 APLL_0 frequency lock Indicates the status of APLL_0. 0 = unlocked. 1 = locked. 2 DPLL_0 frequency lock Indicates the frequency lock status of DPLL_0. 0 = unlocked. 1 = locked. 1 DPLL_0 phase lock Indicates the phase lock status of DPLL_0. 0 = unlocked. 1 = locked. 0 PLL_0 all locked Indicates the status of the system clock, APLL_0, and DPLL_0. 0 = system clock PLL, APLL_0, or DPLL_0 is unlocked. 1 = all three PLLs (system clock PLL, APLL_0, and DPLL_0) are locked. |
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