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AD9554 Datasheet(PDF) 101 Page - Analog Devices |
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AD9554 Datasheet(HTML) 101 Page - Analog Devices |
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101 / 116 page ![]() Data Sheet AD9554 Rev. D | Page 101 of 116 Table 122. IRQ Monitor for Digital PLL2 (DPLL_2) Address Bits Bit Name Description 0x0D11 7 Frequency unclamped IRQ indicating that DPLL_2 has exited a frequency clamped state 6 Frequency clamped IRQ indicating that DPLL_2 has entered a frequency clamped state 5 Phase slew unlimited IRQ indicating that DPLL_2 has exited a phase slew limited state 4 Phase slew limited IRQ indicating that DPLL_2 has entered a phase slew limited state 3 Frequency unlocked IRQ indicating that DPLL_2 has lost frequency lock 2 Frequency locked IRQ indicating that DPLL_2 has acquired frequency lock 1 Phase unlocked IRQ indicating that DPLL_2 has lost phase lock 0 Phase locked IRQ indicating that DPLL_2 has acquired phase lock 0x0D12 7 DPLL_2 switching IRQ indicating that DPLL_2 is switching to a new reference 6 DPLL_2 free run IRQ indicating that DPLL_2 has entered free run mode 5 DPLL_2 holdover IRQ indicating that DPLL_2 has entered holdover mode 4 DPLL_2 history updated IRQ indicating that DPLL_2 has updated its tuning word history 3 REFD activated IRQ indicating that DPLL_2 has activated REFD 2 REFC activated IRQ indicating that DPLL_2 has activated REFC 1 REFB activated IRQ indicating that DPLL_2 has activated REFB 0 REFA activated IRQ indicating that DPLL_2 has activated REFA 0x0D13 7 Phase step direction IRQ indicating that the DPLL_2 demapping controller phase step direction 6 Demap control unclamped IRQ indicating that the DPLL_2 demapping controller is unclamped 5 Demap control clamped IRQ indicating that the DPLL_2 demapping controller is clamped 4 Clock dist sync’d IRQ indicating a distribution sync event 3 APLL_2 unlocked IRQ indicating that APLL_2 has been unlocked 2 APLL_2 locked IRQ indicating that APLL_2 has been locked 1 APLL_2 cal ended IRQ indicating that APLL_2 calibration complete 0 APLL_2 cal started IRQ indicating that APLL_2 calibration started |
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