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AD9554 Datasheet(PDF) 11 Page - Analog Devices |
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AD9554 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 116 page  Data Sheet AD9554 Rev. D | Page 11 of 116 Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT TIMING SKEW Independent of output driver mode; rising edge only; any divide value; negative value means OUTxB is ahead of OUTxA Between OUT0A, OUT0A and OUT0B, OUT0B −60 −6 +48 ps Between OUT1A, OUT1A and OUT1B, OUT1B −60 −6 +48 ps Between OUT2A, OUT2A and OUT2B, OUT2B −60 −6 +48 ps Between OUT3A, OUT3A and OUT3B, OUT3B −60 −6 +48 ps 1 The listed values are for the slower edge (rising or falling). TIME DURATION OF DIGITAL FUNCTIONS Table 9. Parameter Min Typ Max Unit Test Conditions/Comments TIME DURATION OF DIGITAL FUNCTIONS EEPROM to Register Download Time 30 ms Uses default EEPROM storage sequence (see Register 0x0E10 to Register 0x0E6F) assuming full 400 kHz throughput from EEPROM Register to EEPROM Upload Time Varies ms Value dependent on write throughput of the external EEPROM Power-Down Exit Time 51 ms Time from power-down exit to system clock stable (including the system clock stability timer default of 50 ms); does not include time to validate input references or lock the DPLL Mx Pin to RESET Rising Edge Setup Time 1 ns Mx refers to Pin M0 though Pin M9 Mx Pin to RESET Rising Edge Hold Time 1 ns RESET Falling Edge to Mx Pin High-Z Time 10 ns DIGITAL PLL (DPLL_0, DPLL_1, DPLL_2, AND DPLL_3) Table 10. Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL PLL Phase Frequency Detector (PFD) Input Frequency Range 2 200 kHz Loop Bandwidth 0.1 4000 Hz Programmable design parameter; note that (fPFD/loop bandwidth) ≥ 50 Phase Margin 45 89 Degrees Programmable design parameter Closed Loop Peaking <0.1 dB Programmable design parameter; device can be programmed for <0.1 dB peaking in accordance with Telcordia GR-253-CORE jitter transfer ANALOG PLL (APLL_0, APLL_1, APLL_2, AND APLL_3) Table 11. Parameter Min Typ Max Unit Test Conditions/Comments ANALOG PLL0 (APLL_0) VCO Frequency Range 2424 3132 MHz Phase Frequency Detector (PFD) Input Frequency Range 320 350 MHz The AD9554 evaluation software finds the optimal value for this setting based on user input. Loop Bandwidth 240 kHz Phase Margin 68 Degrees ANALOG PLL1 (APLL_1) VCO Frequency Range 3232 3905 MHz Phase Frequency Detector (PFD) Input Frequency Range 320 350 MHz The AD9554 evaluation software finds the optimal value for this setting based on user input. Loop Bandwidth 240 kHz Phase Margin 68 Degrees |
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