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AD9554 Datasheet(PDF) 12 Page - Analog Devices |
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AD9554 Datasheet(HTML) 12 Page - Analog Devices |
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12 / 116 page ![]() AD9554 Data Sheet Rev. D | Page 12 of 116 Parameter Min Typ Max Unit Test Conditions/Comments ANALOG PLL2 (APLL_2) VCO Frequency Range 4842 5650 MHz Phase Frequency Detector (PFD) Input Frequency Range 320 350 MHz The AD9554 evaluation software finds the optimal value for this setting based on user input. Loop Bandwidth 240 kHz Phase Margin 68 Degrees ANALOG PLL3 (APLL_3) VCO Frequency Range 4040 4748 MHz Phase Frequency Detector (PFD) Input Frequency Range 320 350 MHz The AD9554 evaluation software finds the optimal value for this setting based on user input. Loop Bandwidth 240 kHz Phase Margin 68 Degrees DIGITAL PLL LOCK DETECTION Table 12. Parameter Min Typ Max Unit Test Conditions/Comments PHASE LOCK DETECTOR Threshold Programming Range 10 224 − 1 ps Reference-to-feedback phase difference Threshold Resolution 1 ps FREQUENCY LOCK DETECTOR Threshold Programming Range 10 224 − 1 ps Reference-to-feedback period difference Threshold Resolution 1 ps HOLDOVER SPECIFICATIONS Table 13. Parameter Min Typ Max Unit Test Conditions/Comments HOLDOVER SPECIFICATIONS Initial Frequency Accuracy <0.01 ppm Excludes frequency drift of SYSCLK source; excludes frequency drift of input reference prior to entering holdover; compliant with GR-1244 Stratum 3 SERIAL PORT SPECIFICATIONS—SERIAL PORT INTERFACE (SPI) MODE Table 14. Parameter Min Typ Max Unit Test Conditions/Comments CS Valid for VDD_SP = 1.5 V, VDD_SP = 1.8 V, and VDD_SP = 2.5 V Input Logic 1 Voltage VDD_SP − 0.4 V Input Logic 0 Voltage 0.4 V Input Logic 1 Current 1 μA Input Logic 0 Current 1 μA Input Capacitance 3 pF SCLK No internal pull-up or pull-down resistor Input Logic 1 Voltage VDD_SP − 0.4 V Input Logic 0 Voltage 0.4 V Input Logic 1 Current 1 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF |
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