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AD9554

Data Sheet

Rev. D | Page 76 of 116

Table 51. System Clock Stability Period

Address

Bits

Bit Name

Description

0x0206

[7:0]

System clock stability period

(ms), Bits[15:0]

System clock period, Bits[7:0]. The system clock stability period is the amount of time

that the system clock PLL must be locked before it is declared stable. The system clock

stability period is reset automatically if the user writes to this register. The system clock

stability period restarts on the next IO_UPDATE (Register 0x000F = 0x01). Default: 0x32

(0x000032 = 50 ms).

0x0207

[7:0]

System clock period, Bits[15:8]. The system clock stability period is reset automatically if

the user writes to this register. The system clock stability timer restarts on the next

IO_UPDATE (Register 0x000F = 0x01). Default: 0x00.

0x0208

[7:4]

Reserved

Default: 0x0.

[3:0]

System clock stability period,

Bits[19:16]

System clock period, Bits[19:16]. The system clock stability period is reset automatically

if the user writes to this register. The system clock stability period restarts on the next

IO_UPDATE (Register 0x000F = 0x01). Default: 0x0. The units are in milliseconds.

REFERENCE INPUT A (REGISTER 0x0300 TO REGISTER 0x031E)

Table 52. REFA Logic Type

Address

Bits

Bit Name

Description

0x0300

[7:2]

Reserved

Default: 000000b.

[1:0]

REFA logic type, Bits[1:0]

Selects logic family for REFA input receiver; only the REFA pin is used in CMOS mode.

00b (default) = 1.8 V or 1.5 V single-ended CMOS.

01b = ac-coupled differential.

10b = dc-coupled LVDS (fIN ≤ 10.24 MHz).

11b = unused.

Table 53. REFA R Divider (20 Bits) DPLL

Address

Bits

Bit Name

Description

0x0301

[7:0]

R divider, Bits[15:0]

DPLL integer reference divider (minus 1), Bits[7:0]. Default: 0x00. (For example, 0x00000

equals an R divider of 1.)

0x0302

[7:0]

DPLL integer reference divider (minus 1), Bits[15:8]. Default: 0x00.

0x0303

[7:4]

Reserved

Default: 0x0.

[3:0]

R divider, Bits[19:16]

DPLL integer reference divider (minus 1), Bits[19:16]. Default: 0x0.

Table 54. Nominal Period of REFA Input Clock

Address

Bits

Bit Name

Description

0x0304

[7:0]

REFA period (fs), Bits[39:0]

Nominal reference period, Bits[7:0]. Default: 0x00.

0x0305

[7:0]

Nominal reference period, Bits[15:8]. Default: 0x00.

0x0306

[7:0]

Nominal reference period, Bits[23:16]. Default: 0x00.

0x0307

[7:0]

Nominal reference period, Bits[31:24]. Default: 0x00.

0x0308

[7:0]

Nominal reference period, Bits[39:32]. Default: 0x00.

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