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Data Sheet

AD9554

Rev. D | Page 83 of 116

Table 74. Q0_B Divider Setting

Address

Bits

Bit Name

Description

0x043C

[7:0]

Q0_B divider, Bits[7:0]

10-bit channel divider, Bits[7:0] (LSB). Default: 0x00.

Division equals channel divider, Bits[9:0] + 1.

[9:0] = 0 is divide-by-1.

[9:0] = 1 is divide-by-2.

…

[9:0] = 1023 is divide-by-1024.

0x043D

[7:2]

Reserved

Default: 0x00.

[1:0]

Q0_B divider, Bits[9:8]

10-bit channel divider, Bits[9:8] (MSB).

0x043E

[7:6]

Reserved

Default: 0x0.

[5:0]

Q0_B divider phase,

Bits[5:0]

Divider initial phase after sync relative to the divider input clock (from the P0 divider output).

LSB is ½ of a period of the divider input clock. Default: 0x0.

Phase = 0 is no phase offset.

Phase = 1 is ½ a period offset.

DPLL_0 SETTINGS FOR REFERENCE INPUT A (REFA) (REGISTER 0x0440 TO REGISTER 0x044C)

Table 75. DPLL_0 REFA Priority Setting

Address

Bits

Bit Name

Description

0x0440

[7:3]

Reserved

Default: 00000b.

[2:1]

REFA priority

These bits set the priority level (0 to 3) of REFA relative to the other input references.

00 (default) = 0 (highest).

01 = 1.

10 = 2.

11 = 3.

Enable REFA

This bit enables DPLL_0 to lock to REFA.

0 (default) = REFA is not enabled for use by DPLL_0.

1 = REFA is enabled for use by DPLL_0.

Table 76. DPLL_0 REFA Loop Bandwidth Scaling Factor

Address

Bits

Bit Name

Description

0x0441

[7:0]

Digital PLL_0 loop

bandwidth scaling

factor, Bits[15:0] (unit

of 0.1 Hz)

Digital PLL loop bandwidth scaling factor, Bits[7:0]. Default: 0x0.

0x0442

[7:0]

Digital PLL loop bandwidth scaling factor, Bits[15:8]. Default: 0x00. The default for

the DPLL phase detector frequency divided by 50. The DPLL may not lock reliably if the DPLL

loop bandwidth is <50 Hz and a crystal is used for the system clock. See the Choosing the

SYSCLK Source section for details.

0x0443

[7:2]

Reserved

Default: 0x00.

Base loop filter

selection

0 = base loop filter with normal (70°) phase margin (default).

1 = base loop filter with high phase margin. (For loop bandwidth ≤2 kHz, there is ≤0.1 dB

peaking in the closed-loop transfer function. Setting this bit is also recommended for loop

bandwidths >2 kHz.)

Digital PLL_0 loop BW

scaling factor, Bit 16

(unit of 0.1 Hz)

Digital PLL loop bandwidth scaling factor, Bit 16. Default: 0x0.

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