AD9554 datasheet(10/116 Pages) AD

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AD9554

Data Sheet

Rev. D | Page 10 of 116

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Duty Cycle

Up to fOUT = 750 MHz

Up to fOUT = 941 MHz

Up to fOUT = 1250 MHz

Differential Output Voltage Swing

Differential voltage swing between output pins;

measured with output driver static; peak-to-peak

differential output amplitude 2× this level with

driver toggling; see Figure 13 for output

amplitude vs. output frequency

No External Termination Resistor

779

1180

1510

With 50 Ω Termination Resistor to Ground

on Each Leg

413

625

800

Common-Mode Output Voltage

206

312

400

Output driver static with 50 Ω resistor to ground

on each leg

Reference Input-to-Output Delay Variation

over Temperature

600

fs/°C

DPLL locked to same input reference at all times;

stable system clock source (noncrystal)

Static Phase Offset Variation from Active

Reference to Output over Voltage

Extremes

±75

fs/mV

28 mA (LVPECL-COMPATIBLE) MODE

Specifications for dc-coupled, 50 Ω termination

resistor from each leg to ground; ac coupling

used in most applications; output current setting

= 28 mA; in this mode, user must have either a

50 Ω resistor from each leg to ground, or a 100 Ω

resistor across the differential pair

Output Frequency

0.430

941

MHz

Frequency range all four PLLs can be generated

using unique VCO frequencies; frequencies

outside this range are possible on some of the PLLs,

but can result in increased VCO coupling due to

multiple PLLs using the same VCO frequency

Continuous Output Frequency Range

0.430

781

MHz

Frequency range for each PLL such that all four

PLLs are using unique VCO frequencies with no

frequency gaps

Maximum Output Frequency

PLL0 to PLL3 Using Unique VCO

Frequencies

941

MHz

Maximum frequency all four PLLs can generate

using unique VCO frequencies

PLL0, PLL1, and PLL2

1250

MHz

Limited by 1250 MHz maximum input frequency

to channel divider (Q divider)

PLL3

1187

MHz

Limited by 4748 MHz maximum VCO frequency

Rise/Fall Time (20% to 80%)1

185

280

Duty Cycle

Up to fOUT = 750 MHz

Up to fOUT = 941 MHz

Up to fOUT = 1250 MHz

Differential Output Voltage Swing

540

830

1020

Differential voltage swing between output pins;

measured with output driver static; peak-to-peak

differential output amplitude 2× this level with

driver toggling; see Figure 10 for output

amplitude vs. output frequency

Common-Mode Output Voltage

275

415

510

Output driver static; 50 Ω external termination

resistor from each leg to ground

Reference Input-to-Output Delay Variation

over Temperature

600

fs/°C

DPLL locked to same input reference at all times;

stable system clock source (noncrystal)

Static Phase Offset Variation from Active

Reference to Output over Voltage

Extremes

±75

fs/mV

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