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AD9554 Datasheet(PDF) 7 Page - Analog Devices |
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AD9554 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 116 page  Data Sheet AD9554 Rev. D | Page 7 of 116 Parameter Min Typ Max Unit Test Conditions/Comments Input Capacitance 3 pF Single-ended to ground, each pin Input Resistance 5 kΩ CRYSTAL RESONATOR PATH Crystal Resonator Frequency Range 12 50 MHz Fundamental mode, AT cut crystal Input Capacitance 3 pF Single-ended to ground, each pin Maximum Crystal Motional Resistance 100 Ω REFERENCE INPUTS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments DIFFERENTIAL MODE AC couple inputs in differential mode Frequency Range Sinusoidal Input 10 475 MHz LVPECL Input 0.002 1000 MHz LVDS Input 0.002 700 MHz Assumes an LVDS minimum of 494 mV p-p differential amplitude Minimum Input Slew Rate Minimum limit imposed for jitter performance DPLL Loop Bandwidth = 50 Hz 40 V/μs DPLL Loop Bandwidth = 4 kHz 50 V/μs Maximum loop bandwidth is fPFD/50 Common-Mode Input Voltage 0.64 V Internally generated self-bias voltage Differential Input Voltage Sensitivity Peak-to-peak differential voltage swing across pins required to ensure switching between logic levels as measured with a differential probe; instantaneous voltage on either pin must not exceed 1.3 V fIN < 400 MHz 400 2100 mV p-p fIN = 400 MHz to 750 MHz 500 2100 mV p-p fIN = 750 MHz to 1000 MHz 1000 2100 mV p-p Differential Input Voltage Hysteresis 55 100 mV Input Resistance 16 kΩ Equivalent differential input resistance Input Capacitance 9 pF Single-ended to ground, each pin Minimum Pulse Width High LVPECL 460 ps LVDS 560 ps Minimum Pulse Width Low LVPECL 460 ps LVDS 560 ps DC-COUPLED LVDS MODE Intended for dc-coupled LVDS ≤10.24 MHz Frequency Range 0.002 10.24 MHz Minimum Input Slew Rate Minimum limit imposed for jitter performance DPLL Loop Bandwidth = 50 Hz 40 V/μs DPLL Loop Bandwidth = 4 kHz 150 V/μs Maximum loop bandwidth is fPFD/50 Common-Mode Input Voltage 1.125 1.375 V Differential Input Voltage Sensitivity 400 1200 mV Differential voltage across pins required to ensure switching between logic levels; instantaneous voltage on either pin must not exceed the supply rails Differential Input Voltage Hysteresis 55 100 mV Input Resistance 21 kΩ Input Capacitance 7 pF Minimum Pulse Width High 25 ns Minimum Pulse Width Low 25 ns |
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