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AD9554 Datasheet(PDF) 63 Page - Analog Devices |
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AD9554 Datasheet(HTML) 63 Page - Analog Devices |
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63 / 116 page ![]() Data Sheet AD9554 Rev. D | Page 63 of 116 Reg Addr (Hex) Option Name D7 D6 D5 D4 D3 D2 D1 D0 Def (Hex) DPLL_0 Settings for Reference Input D 0x0467 Reference priority Reserved REFD priority Enable REFD 0x00 0x0468 W2, L DPLL_0 loop BW (17 bits) Digital PLL_0 loop bandwidth scaling factor, Bits[7:0] (unit: 0.1 Hz) 0x00 0x0469 W2, L Digital PLL_0 loop bandwidth scaling factor, Bits[15:8] (unit: 0.1 Hz) 0x00 0x046A W2, L Reserved Base loop filter selection Digital PLL_0 loop BW scaling factor, Bit 16 0x00 0x046B W2 DPLL_0 N0 divider (18 bits) Digital PLL_0 feedback divider—Integer Part N0, Bits[7:0] 0x00 0x046C W2 Digital PLL_0 feedback divider—Integer Part N0, Bits[15:8] 0x00 0x046D W2 Reserved Digital PLL_0 feedback divider—Integer Part N0, Bits[17:16] 0x00 0x046E W8 DPLL_0 fractional feedback divider (24 bits) Digital PLL_0 fractional feedback divider—FRAC0, Bits[7:0] 0x00 0x046F W8 Digital PLL_0 fractional feedback divider—FRAC0, Bits[15:8] 0x00 0x0470 W8 Digital PLL_0 fractional feedback divider—FRAC0, Bits[23:16] 0x00 0x0471 W2 DPLL_0 fractional feedback divider modulus (24 bits) Digital PLL_0 feedback divider modulus—MOD0, Bits[7:0] 0x00 0x0472 W2 Digital PLL_0 feedback divider modulus—MOD0, Bits[15:8] 0x00 0x0473 W2 Digital PLL_0 feedback divider modulus—MOD0, Bits[23:16] 0x00 DPLL_1 General Settings 0x0500 to 0x051E These registers mimic the DPLL_0 general settings registers (0x0400 through 0x041E) but the register addresses are offset by 0x0100. All default values are identical. Output PLL_1 (APLL_1) and Channel 1 Output Drivers 0x0530 to 0x053E These registers mimic the output PLL_0 (APLL_0) general settings registers (0x0430 through 0x043E) but the register addresses are offset by 0x0100. All default values are identical. DPLL_1 Settings for Reference Input A 0x0540 to 0x054C These registers mimic the DPLL_0 settings for Reference Input A registers (0x0440 through 0x044C) but the register addresses are offset by 0x0100. All default values are identical. DPLL_1 Settings for Reference Input B 0x054D to 0x0559 These registers mimic the DPLL_0 settings for Reference Input B registers (0x044D through 0x0459) but the register addresses are offset by 0x0100. All default values are identical. DPLL_1 Settings for Reference Input C 0x055A to 0x0566 These registers mimic the DPLL_0 settings for Reference Input C registers (0x045A through 0x0466) but the register addresses are offset by 0x0100. All default values are identical. DPLL_1 Settings for Reference Input D 0x0567 to 0x0573 These registers mimic the DPLL_0 settings for Reference Input D registers (0x0467 through 0x0473) but the register addresses are offset by 0x0100. All default values are identical. DPLL_2 General Settings 0x0600 to 0x061E These registers mimic the DPLL_0 general settings registers (0x0400 through 0x041E) but the register addresses are offset by 0x0200. All default values are identical. Output PLL_2 (APLL_2) and Channel 2 Output Drivers 0x0630 to 0x063E These registers mimic the output PLL_0 (APLL_0) general settings registers (0x0430 through 0x043E) but the register addresses are offset by 0x0200. All default values are identical. DPLL_2 Settings for Reference Input A 0x0640 to 0x064C These registers mimic the DPLL_0 settings for Reference Input A registers (0x0440 through 0x044C) but the register addresses are offset by 0x0200. All default values are identical. |
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