 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD9554 Datasheet(PDF) 94 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9554 Datasheet(HTML) 94 Page - Analog Devices |
|
|
94 / 116 page  AD9554 Data Sheet Rev. D | Page 94 of 116 Address Bits Bit Name Description 0x0A0E 7 Phase step detected Clears IRQ indicating that DPLL_1 has detected a large phase step at its input 6 Demap control unclamped Clears IRQ indicating that the DPLL_1 demapping controller has an unclamped state 5 Demap control clamped Clears IRQ indicating that the DPLL_1 demapping controller has a clamped state 4 Clock dist sync’d Clears IRQ indicating a distribution sync event 3 APLL_1 unlocked Clears IRQ indicating that APLL_1 has been unlocked 2 APLL_1 locked Clears IRQ indicating that APLL_1 has been locked 1 APLL_1 cal ended Clears IRQ indicating that APLL_1 calibration complete 0 APLL_1 cal started Clears IRQ indicating that APLL_1 calibration started Table 108. IRQ Clearing for Digital PLL2 (DPLL_2) Address Bits Bit Name Description 0x0A0F 7 Frequency unclamped Clears IRQ indicating that DPLL_2 has exited a frequency unclamped state 6 Frequency clamped Clears IRQ indicating that DPLL_2 has entered a frequency clamped state 5 Phase slew unlimited Clears IRQ indicating that DPLL_2 has exited a phase slew limited state 4 Phase slew limited Clears IRQ indicating that DPLL_2 has entered a phase slew limited state 3 Frequency unlocked Clears IRQ indicating that DPLL_2 has lost frequency lock 2 Frequency locked Clears IRQ indicating that DPLL_2 has acquired frequency lock 1 Phase unlocked Clears IRQ indicating that DPLL_2 has lost phase lock 0 Phase locked Clears IRQ indicating that DPLL_2 has acquired phase lock 0x0A10 7 DPLL_2 switching Clears IRQ indicating that DPLL_2 is switching to a new reference 6 DPLL_2 free run Clears IRQ indicating that DPLL_2 has entered free run mode 5 DPLL_2 holdover Clears IRQ indicating that DPLL_2 has entered holdover mode 4 History updated Clears IRQ indicating that DPLL_2 has updated its tuning word history 3 REFD activated Clears IRQ indicating that DPLL_2 has activated REFD 2 REFC activated Clears IRQ indicating that DPLL_2 has activated REFC 1 REFB activated Clears IRQ indicating that DPLL_2 has activated REFB 0 REFA activated Clears IRQ indicating that DPLL_2 has activated REFA 0x0A11 7 Phase step detected Clears IRQ indicating that DPLL_2 has detected a large phase step at its input 6 Demap control unclamped Clears IRQ indicating that the DPLL_2 demapping controller is unclamped 5 Demap control clamped Clears IRQ indicating that the DPLL_2 demapping controller is clamped 4 Clock dist sync’d Clears IRQ indicating a distribution sync event 3 APLL_2 unlocked Clears IRQ indicating that APLL_2 has been unlocked 2 APLL_2 locked Clears IRQ indicating that APLL_2 has been locked 1 APLL_2 cal ended Clears IRQ indicating that APLL_2 calibration complete 0 APLL_2 cal started Clears IRQ indicating that APLL_2 calibration started |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
