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AD9136-EBZ Datasheet(PDF) 102 Page - Analog Devices |
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AD9136-EBZ Datasheet(HTML) 102 Page - Analog Devices |
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102 / 117 page  AD9135/AD9136 Data Sheet Rev. C | Page 102 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x203 GENERIC_PD [7:2] RESERVED Reserved. 0x0 R 1 SPI_SYNC1_PD Power down LVDS buffer for SYNCOUT0±. 0x0 R/W 0 SPI_SYNC2_PD Power down LVDS buffer for SYNCOUT1±. 0x0 R/W 0x206 CDR_RESET [7:1] RESERVED Reserved. 0x0 R 0 SPI_CDR_RESETN Resets the Digital Control Logic for All PHYs. 0x1 R/W 0 Hold CDR in reset 1 Enable CDR 0x230 CDR_OPERATING_ MODE_REG_0 [7:6] RESERVED Reserved. 0x0 R 5 ENHALFRATE Enables Half-Rate CDR Operation. Set to 1 when 5.75 Gbps ≤ lane rate ≤ 12.4 Gbps. 0x1 R/W [4:2] RESERVED Must write the default value for proper operation. 0x2 R/W 1 CDR_OVERSAMP Enables Oversampling of the Input Data. Set to 1 when 1.44 Gbps ≤ lane rate ≤ 3.1 Gbps. 0x0 R/W 0 RESERVED Reserved. 0x0 R 0x232 DEVICE_CONFIG_ REG_3 [7:0] DEVICE_CONFIG_3 Must be set to 0xFF for proper JESD interface configuration. 0x0 R/W 0x268 EQ_BIAS_REG [7:6] EQ_POWER_ MODE Control the Equalizer Power/Insertion Loss Capability. 0x1 R/W 00 Normal mode 01 Low power mode [5:0] RESERVED Must write the default value for proper operation. 0x22 R/W 0x280 SERDESPLL_ ENABLE_CNTRL [7:3] RESERVED Reserved. 0x0 R 2 RECAL_SERDESPLL Recalibrate SERDES PLL. On a rising edge, recalibrate the SERDES PLL. 0x0 R/W 1 RESERVED Reserved. 0x0 R 0 ENABLE_ SERDESPLL Enable the SERDES PLL. Setting this bit enables and calibrates the SERDES PLL. 0x0 R/W 0x281 PLL_STATUS [7:6] RESERVED Reserved. 0x0 R 5 SERDES_PLL_ OVERRANGE_H SERDES PLL High Overrange. This bit indicates that the SERDES PLL hit the lower edge of its operating band. Recalibrate. 0x0 R 4 SERDES_PLL_ OVERRANGE_L SERDES PLL Low Overrange. This bit indicates that the SERDES PLL hit the lower edge of its operating band. Recalibrate. 0x0 R 3 SERDES_PLL_CAL_ VALID_RB SERDES PLL Calibration Valid. This bit indicates that the SERDES PLL has been successfully calibrated. 0x0 R [2:1] RESERVED Reserved. 0x0 R 0 SERDES_PLL_ LOCK_RB SERDES PLL Lock. This bit is set high by the PLL when it has achieved lock. 0x0 R 0x284 LOOP_FILTER_1 [7:0] LOOP_FILTER_1 SERDES PLL loop filter setting. This register must be written to 0x62 for optimal performance. 0x77 R/W 0x285 LOOP_FILTER_2 [7:0] LOOP_FILTER_2 SERDES PLL loop filter setting. This register must be written to 0xC9 for optimal performance. 0x87 R/W 0x286 LOOP_FILTER_3 [7:0] LOOP_FILTER_3 SERDES PLL loop filter setting. This register must be written to 0x0E for optimal performance. 0x08 R/W 0x287 SERDES_PLL_CP1 [7:0] SERDES_PLL_CP1 SERDES PLL charge pump setting. This register must be written to 0x12 for optimal performance. 0x3F R/W |
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