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AD9136-EBZ Datasheet(PDF) 106 Page - Analog Devices |
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AD9136-EBZ Datasheet(HTML) 106 Page - Analog Devices |
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106 / 117 page  AD9135/AD9136 Data Sheet Rev. C | Page 106 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x30D FIFO_STATUS_REG_1 [7:0] LANE_FIFO_EMPTY FIFO Empty Flags for Each Logical Lane. An empty FIFO indicates an error in the JESD204B configuration or with a system clock. 0x0 R If the FIFO for Logical Lane x is empty, Bit x in this register will be high. 0x312 SYNCB_GEN_1 [7:6] RESERVED Reserved. 0x0 R/W [5:4] SYNCB_ERR_DUR Duration of SYNCOUTx± Low for Error. The duration applies to both SYNCOUT0 and SYNCOUT1. A sync error is asserted at the end of a multiframe whenever one or more disparity, not in table or unexpected control character errors are encountered. 0 ½ PCLK cycle 1 1 PCLK cycle 2 2 PCLK cycles [3:0] RESERVED Reserved. 0x0 R/W 0x314 SERDES_SPI_REG [7:0] SERDES_SPI_ CONFIG SERDES SPI Configuration. Must be written to 0x01 as part of the Physical Layer setup step. 0x0 R/W 0x315 PHY_PRBS_TEST_EN [7:0] PHY_TEST_EN PHY Test Enable. Enables the PHY BER test. 0x0 R/W Set Bit x to enable the PHY test for Lane x. 0x316 PHY_PRBS_TEST_CTRL 7 RESERVED Reserved. 0x0 R [6:4] PHY_SRC_ERR_CNT PHY Error Count Source. Selects which PHY errors are being reported in Register 0x31A to Register 0x31C. 0x0 R/W x Report Lane x error count [3:2] PHY_PRBS_PAT_SEL PHY PRBS Pattern Select. Selects the PRBS pattern for PHY BER test. 0x0 R/W 00 PRBS7 01 PRBS15 10 PRBS31 1 PHY_TEST_START PHY PRBS Test Start. Starts and stops the PHY PRBS test. 0x0 R/W 0 Test stopped 1 Test in progress 0 PHY_TEST_RESET PHY PRBS Test Reset. Resets the PHY PRBS test state machine and error counters. 0x0 R/W 0 Enable PHY PRBS test state machine 1 Hold PHY PRBS test state machine in reset 0x317 PHY_PRBS_TEST_ THRESHOLD_LOBITS [7:0] PHY_PRBS_ THRESHOLD[7:0] 8 LSBs of PHY PRBS Error Threshold. 0x0 R/W 0x318 PHY_PRBS_TEST_ THRESHOLD_ MIDBITS [7:0] PHY_PRBS_ THRESHOLD[15:8] 8 ISBs of PHY PRBS Error Threshold. 0x0 R/W 0x319 PHY_PRBS_TEST_ THRESHOLD_HIBITS [7:0] PHY_PRBS_ THRESHOLD[23:16] 8 MSBs of PHY PRBS Error Threshold. 0x0 R/W 0x31A PHY_PRBS_TEST_ ERRCNT_LOBITS [7:0] PHY_PRBS_ERR_ CNT[7:0] 8 LSBs of PHY PRBS Error Count. Reported PHY BERT error count from lane selected using Register 0x316[6:4]. 0x0 R 0x31B PHY_PRBS_TEST_ ERRCNT_MIDBITS [7:0] PHY_PRBS_ERR_ CNT[15:8] 8 ISBs of PHY PRBS Error Count. 0x0 R 0x31C PHY_PRBS_TEST_ ERRCNT_HIBITS [7:0] PHY_PRBS_ERR_ CNT[23:16] 8 MSBs of PHY PRBS Error Count. 0x0 R 0x31D PHY_PRBS_TEST_ STATUS [7:0] PHY_PRBS_PASS PHY PRBS Test Pass/Fail. 0xFF R Bit x corresponds to PHY PRBS pass/fail for Physical Lane x. The bit is set to 1 while the error count for Physical Lane x is less than PHY_PRBS_THRESHOLD. |
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