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AD9136-EBZ Datasheet(PDF) 110 Page - Analog Devices

Part # AD9136-EBZ
Description  Digital-to-Analog Converters
PDF  117 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9136-EBZ Datasheet(HTML) 110 Page - Analog Devices

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AD9135/AD9136
Data Sheet
Rev. C | Page 110 of 117
Address
Name
Bit No.
Bit Name
Settings
Description
Reset
Access
0x42A
LID4_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LID4_RD
Lane Identification for Link Lane 4.
0x0
R
0x42D
CHECKSUM4_REG
[7:0]
FCHK4_RD
Checksum for Link Lane 4.
0x0
R
0x42E
COMPSUM4_REG
[7:0]
FCMP4_RD
Computed Checksum for Link Lane 4 (see the
description for Register 0x40E).
0x0
R
0x432
LID5_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LID5_RD
Lane Identification for Link Lane 5.
0x0
R
0x435
CHECKSUM5_REG
[7:0]
FCHK5_RD
Checksum for Link Lane 5.
0x0
R
0x436
COMPSUM5_REG
[7:0]
FCMP5_RD
Computed Checksum for Link Lane 5 (see the
description for Register 0x40E).
0x0
R
0x43A
LID6_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LID6_RD
Lane Identification for Link Lane 6.
0x0
R
0x43D
CHECKSUM6_REG
[7:0]
FCHK6_RD
Checksum for Link Lane 6.
0x0
R
0x43E
COMPSUM6_REG
[7:0]
FCMP6_RD
Computed Checksum for Link Lane 6 (see the
description for Register 0x40E).
0x0
R
0x442
LID7_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LID7_RD
Lane Identification for Link Lane 7.
0x0
R
0x445
CHECKSUM7_REG
[7:0]
FCHK7_RD
Checksum for Link Lane 7.
0x0
R
0x446
COMPSUM7_REG
[7:0]
FCMP7_RD
Computed Checksum for Link Lane 7 (see the
description for Register 0x40E).
0x0
R
0x450
ILS_DID
[7:0]
DID
Device Identification Number. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B. Must be set to value
read in Register 0x400.
0x0
R/W
0x451
ILS_BID
[7:4]
ADJCNT
Adjustment Resolution to DAC LMFC Must
be set to 0.
0x0
R/W
[3:0]
BID
Bank Identification: Extension to DID Must be
set to value read in Register 0x401[3:0].
0x0
R/W
0x452
ILS_LID0
7
RESERVED
Reserved.
0x0
R
6
ADJDIR
Direction to Adjust DAC LMFC. Must be set to 0.
0x0
R/W
5
PHADJ
Phase Adjustment Request to DAC. Must be
set to 0.
0x0
R/W
[4:0]
LID0
Lane Identification for Link Lane 0. Must be set
to the value read in Register 0x402[4:0].
0x0
R/W
0x453
ILS_SCR_L
7
SCR
Receiver Descrambling Enable.
0x1
R/W
0
Descrambling is disabled
1
Descrambling is enabled
[6:5]
RESERVED
Reserved.
0x0
R
[4:0]
L-1
Number of Lanes per Converter Device. See
Table 34 and Table 35.
0x3
R/W
0
One lane per converter
1
Two lanes per converter
3
Four lanes per converter
7
Eight lanes per converter (single link only)
0x454
ILS_F
[7:0]
F-1
Number of Octets per Lane per Frame. Settings
of 1, 2, and 4 (octets per lane) per frame are
valid. See Table 34 and Table 35.
0x0
R/W
0
(One octet per lane) per frame
1
(Two octets per lane) per frame
3
(Four octets per lane) per frame
0x455
ILS_K
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
K-1
Number of Frames per Multiframe. Settings
of 16 or 32 are valid. Must be set to 32 when
F = 1 (Register 0x476).
0x1F
R/W
0x0F
16 frames per multiframe
0x1F
32 frames per multiframe



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