AD9136-EBZ datasheet(112/117 Pages) AD

112 / 117 page

AD9135/AD9136

Data Sheet

Rev. C | Page 112 of 117

Address

Name

Bit No.

Bit Name

Settings

Description

Reset

Access

0x46D

BADDISPARITY

RST_IRQ_DIS

BADDIS IRQ Reset. Reset BADDIS IRQ for lane

selected via Bits[2:0] by writing 1 to this bit.

0x0

DISABLE_ERR_

CNTR_DIS

BADDIS Error Counter Disable. Disable the

BADDIS error counter for lane selected via

Bits[2:0] by writing 1 to this bit.

0x0

RST_ERR_CNTR_DIS

BADDIS Error Counter Reset. Reset BADDIS

error counter for lane selected via Bits[2:0] by

writing 1 to this bit.

0x0

[4:3]

RESERVED

Reserved.

0x0

[2:0]

LANE_ADDR_DIS

Link Lane Address for Functions Described in

Bits[7:5].

0x0

0x46E

NIT_RB

[7:0]

NIT

Not in table Character Error (NIT). Bit x is set

when Link Lane x’s NIT error count reaches

the threshold in Register 0x47C.

0x0

0x46E

NIT_W

RST_IRQ_NIT

IRQ Reset. Reset IRQ for lane selected via

Bits[2:0] by writing 1 to this bit.

0x0

DISABLE_ERR_

CNTR_NIT

Disable Error Counter. Disable the error

counter for lane selected via Bits[2:0] by

writing 1 to this bit.

0x0

RST_ERR_CNTR_NIT

Reset Error Counter. Reset error counter for lane

selected via Bits[2:0] by writing 1 to this bit.

0x0

[4:3]

RESERVED

Reserved.

0x0

[2:0]

LANE_ADDR_NIT

Link Lane Address for Functions Described in

Bits[7:5].

0x0

0x46F

UNEXPECTED-

CONTROL_RB

[7:0]

UCC

Unexpected Control Character Error (UCC).

Bit x is set when Link Lane x’s UCC error

count reaches the threshold in Register 0x47C.

0x0

0x46F

UNEXPECTED-

CONTROL_W

RST_IRQ_UCC

IRQ Reset. Reset IRQ for lane selected via

Bits[2:0] by writing 1 to this bit.

0x0

DISABLE_ERR_

CNTR_UCC

Disable Error Counter. Disable the error

counter for lane selected via Bits[2:0] by

writing 1 to this bit.

0x0

RST_ERR_CNTR_

UCC

Reset Error Counter. Reset error counter for

lane selected via Bits[2:0] by writing 1 to this bit.

0x0

[4:3]

RESERVED

Reserved.

0x0

[2:0]

LANE_ADDR_UCC

Link Lane Address for Functions Described in

Bits[7:5].

0x0

0x470

CODEGRPSYNCFLG

[7:0]

CODEGRPSYNC

Code Group Sync Flag (from Each Instantiated

Lane). Writing 1 to Bit 7 resets the IRQ. The

associated IRQ flag is located in Register

0x47A[0]. A loss of CODEGRPSYNC triggers

sync request assertion. See the SYNCOUTx±,

SYSREF±, and CLK± Signals section and the

Deterministic Latency section.

0x0

R/W

Synchronization is lost

Synchronization is achieved

0x471

FRAMESYNCFLG

[7:0]

FRAMESYNC

Frame Sync Flag (from Each Instantiated

Lane). This register indicates the live status

for each lane. Writing 1 to Bit 7 resets the

IRQ. A loss of frame sync automatically

initiates a synchronization sequence.

0x0

R/W

Synchronization is lost

Synchronization is achieved

0x472

GOODCHKSUMFLG

[7:0]

GOODCHECKSUM

Good Checksum Flag (from Each Instantiated

Lane). Writing 1 to Bit 7 resets the IRQ.

The associated IRQ flag is located in

0x0

R/W

Last computed checksum is not correct

Last computed checksum is correct

AD9136-EBZ Datasheet(PDF) 112 Page - Analog Devices

AD9136-EBZ Datasheet(HTML) 112 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL