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AD9136-EBZ Datasheet(PDF) 111 Page - Analog Devices |
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AD9136-EBZ Datasheet(HTML) 111 Page - Analog Devices |
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111 / 117 page  Data Sheet AD9135/AD9136 Rev. C | Page 111 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x456 ILS_M [7:0] M-1 Number of Converters per Device. See Table 34 and Table 35. 0x1 R/W 0 One converter per link 1 Two converters per link 0x457 ILS_CS_N [7:6] CS Number of Control Bits per Sample. Must be set to 0. Control bits are not supported. 0x0 R/W 0 Zero control bits per sample 5 RESERVED Reserved. 0x0 R [4:0] N-1 Converter Resolution. Must be set to 16 bits of resolution. 0xF R/W 0x0F Converter resolution of 16. 0x458 ILS_NP [7:5] SUBCLASSV Device Subclass Version. 0x1 R/W 0 Subclass 0 1 Subclass 1 [4:0] NP-1 Total Number of Bits per Sample. Must be set to 16 bits per sample. 0xF R/W 0xF 16 bits per sample. 0x459 ILS_S [7:5] JESDV JESD204 Version. 0x1 R/W 000 JESD204A 001 JESD204B [4:0] S-1 Number of Samples per Converter per Frame Cycle. Settings of one and two are valid. 0x0 R/W 0 One sample per converter per frame 1 Two samples per converter per frame 0x45A ILS_HD_CF 7 HD High Density Format. If F = 1, HD must be set to 1. Otherwise, HD must be set to 0. See Section 5.1.3 of JESD204B standard. 0x1 R/W 0 Low density mode 1 High density mode [6:5] RESERVED Reserved. 0x0 R [4:0] CF Number of Control Words per Frame Clock Period per Link. Must be set to 0. Control bits are not supported. 0x0 R/W 0x45B ILS_RES1 [7:0] RES1 Reserved Field 1. 0x0 R/W 0x45C ILS_RES2 [7:0] RES2 Reserved Field 2. 0x0 R/W 0x45D ILS_CHECKSUM [7:0] FCHK0 Checksum for Link Lane 0. Calculated checksum. Calculation depends on 0x300[6]. 0x45 R/W 0x46B ERRCNTRMON_RB [7:0] READERRORCNTR Read JESD204B Error Counter. After selecting the lane and error counter by writing to LANESEL and CNTRSEL (both in this same register), the selected error counter is read back here. 0x0 R 0x46B ERRCNTRMON 7 RESERVED Reserved. 0x0 R [6:4] LANESEL Link Lane select for JESD204B error counter. Selects the lane whose errors are read back in this register. 0x0 W x Selects Link Lane x [3:2] RESERVED Reserved. 0x0 R [1:0] CNTRSEL JESD204B Error Counter Select. Selects the type of error that are read back in this register. 0x0 W 00 BADDISCNTR: bad running disparity counter 01 NITCNTR: not in table error counter 10 UCCCNTR: Unexpected control character counter 0x46C LANEDESKEW [7:0] LANEDESKEW Lane Deskew. Setting Bit x deskews Link Lane x 0xF R/W 0x46D BADDISPARITY_RB [7:0] BADDIS Bad Disparity Character Error (BADDIS). Bit x is set when the bad disparity error count for Link Lane x reaches the threshold in Register 0x47C. 0x0 R |
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