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AD9136-EBZ Datasheet(PDF) 107 Page - Analog Devices |
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AD9136-EBZ Datasheet(HTML) 107 Page - Analog Devices |
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107 / 117 page  Data Sheet AD9135/AD9136 Rev. C | Page 107 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x32C SHORT_TPL_TEST_0 [7:6] RESERVED Reserved. 0x0 R [5:4] SHORT_TPL_SP_ SEL Short Transport Layer Sample Select. Selects which sample to check from the DAC selected via Bits[3:2]. 0x0 R/W x Sample x [3:2] SHORT_TPL_DAC_ SEL Short Transport Layer Test DAC Select. Selects which DAC to sample. 0x0 R/W 0 Sample from DAC0 2 Sample from DAC1 1 SHORT_TPL_TEST_ RESET Short Transport Layer Test Reset. Resets the result of short transport layer test. 0x0 R/W 0 Not reset 1 Reset 0 SHORT_TPL_TEST_ EN Short Transport Layer Test Enable. See the Subclass 0 section for details on how to perform this test. 0x0 R/W 0 Disable 1 Enable 0x32D SHORT_TPL_TEST_1 [7:0] SHORT_TPL_REF_ SP_LSB Short Transport Layer Test Reference, Sample LSB. This is the lower eight bits of the expected DAC sample. It is used to compare with the received DAC sample at the output of the JESD204B receiver. 0x0 R/W 0x32E SHORT_TPL_TEST_2 [7:0] SHORT_TPL_REF_ SP_MSB Short Transport Layer Test Reference, Sample MSB. This is the upper eight bits of the expected DAC sample. It is used to compare with the received DAC sample at the output of the JESD204B receiver. 0x0 R/W 0x32F SHORT_TPL_TEST_3 [7:1] RESERVED Reserved. 0x0 R 0 SHORT_TPL_FAIL Short Transport Layer Test Fail. This bit shows whether the selected DAC sample matches the reference sample. If they match, it is a test pass, otherwise it is a test fail. 0x0 R 0 Test pass 1 Test fail 0x333 DEVICE_CONFIG_ REG_13 [7:0] DEVICE_CONFIG_ 13 Must be set to 0x01 for proper JESD interface configuration. 00 R/W 0x334 JESD_BIT_INVERSE_ CTRL [7:0] JESD_BIT_INVERSE Logical Lane Invert. Set Bit x high to invert the JESD deserialized data on Logical Lane x. 0x0 R/W 0x400 DID_REG [7:0] DID_RD Device Identification Number. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R 0x401 BID_REG [7:4] ADJCNT_RD Adjustment Resolution to DAC LMFC. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 0. 0x0 R [3:0] BID_RD Bank Identification: Extension to DID. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R 0x402 LID0_REG 7 RESERVED Reserved. 0x0 R 6 ADJDIR_RD Direction to Adjust DAC LMFC. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 0. 0x0 R 5 PHADJ_RD Phase Adjustment Request to DAC Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 0. 0x0 R [4:0] LID0_RD Lane Identification for Lane 0. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R |
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