 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD9136-EBZ Datasheet(PDF) 104 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9136-EBZ Datasheet(HTML) 104 Page - Analog Devices |
|
|
104 / 117 page  AD9135/AD9136 Data Sheet Rev. C | Page 104 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x2AE TERM_BLK2_ CTRLREG0 [7:1] RESERVED Reserved. 0x0 R 0 RCAL_TERMBLK2 Terminal Calibration. The rising edge of this bit calibrates PHY2, PHY3, PHY4 and PHY5 terminations to 50 Ω. 0x0 R/W 0x2B1 DEVICE_CONFIG_ REG_11 [7:0] DEVICE_CONFIG_ 11 Must be set to 0xB7 for proper JESD interface termination configuration. 0xC3 R/W 0x2B2 DEVICE_CONFIG_ REG_12 [7:0] DEVICE_CONFIG_ 12 Must be set to 0x87 for proper JESD interface termination configuration. 0x93 R/W 0x300 GENERAL_JRX_ CTRL_0 7 RESERVED Reserved. 0x0 R 6 CHECKSUM_MODE Checksum Mode. This bit controls the locally generated JESD204B link parameter checksum method. The value is stored in the FCMP registers (Register 0x40E, Register 0x416, Register 0x41E, Register 0x426, Register 0x42E, Register 0x436, Register 0x43E, and Register 0x446). 0x0 R/W 0 Checksum is calculated by summing the individual fields in the link configuration table as defined in Section 8.3, Table 20 of the JESD204B standard 1 Checksum is calculated by summing the regis- ters containing the packed link configuration fields (Σ[0x400:0x40A] modulo 256). [5:4] RESERVED Reserved. 0x0 R 3 LINK_MODE Link Mode. This register selects either single- link or dual-link mode. 0x0 R/W 0 Single-link mode 1 Dual-link mode 2 LINK_PAGE Link Paging. Selects which link’s register map is used. This paging affects Registers 0x401 to 0x47E. 0x0 R/W 0 Use Link 0 register map 1 Use Link 1 register map [1:0] LINK_EN Link Enable. These bits bring up the JESD204B receiver digital circuitry: Bit 0 for Link 0 and Bit 1 for Link 1. Enable the link only after the following has occurred: all JESD204B para- meters are set, the DAC PLL is enabled and locked (Register 0x084[1] = 1), and the JESD204B PHY is enabled (Register 0x200 = 0x00) and calibrated (Register 0x281[2] = 0). 0x0 R/W 0b00 Disable both JESD Link 1 and JESD Link 0 0b01 Disable JESD Link 1, enable JESD Link 0 0b10 Enable JESD Link 1, disable JESD Link 0 0b11 Enable both JESD Link 1 and JESD Link 0 0x301 GENERAL_JRX_CTRL_1 [7:3] RESERVED Reserved. 0x0 R [2:0] SUBCLASSV_ LOCAL JESD204B Subclass. 0x1 R/W 000 Subclass 0 001 Subclass 1 0x302 DYN_LINK_LATENCY_0 [7:5] RESERVED Reserved. 0x0 R [4:0] DYN_LINK_ LATENCY_0 Dynamic Link Latency: Link 0. Latency between the LMFCRx for Link 0 and the last arriving LMFC boundary in units of PCLK cycles. See the Deterministic Latency section. 0x0 R 0x303 DYN_LINK_LATENCY_1 [7:5] RESERVED Reserved. 0x0 R [4:0] DYN_LINK_ LATENCY_1 Dynamic Link Latency: Link 1. Latency between the LMFCRx for Link 1 and the last arriving LMFC boundary in units of PCLK cycles. See the Deterministic Latency section. 0x0 R |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
