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PAD ASSIGNMENT TABLES
PRELIMINARY V1.8
121
TABLE 84.
Standard 52 Pin Device Chip
P4.0
RFPWR
io3
RF power switch output/ I/O
P4.1
PLLSW
io3
Phase-lock loop switch output/ I/O
P3.3
TXEN
io3
Transmitter enable output/ I/O
P3.2
CPTRD1
io3
Capture Timer 1/Down Counter
P3.1
CPTRU1
io3
Capture Timer 1
P3.0
CPTRU2
io3
Capture Timer 2
P1.5
SPIO
io3
Serial Out
P1.6
SPIIN
io3
Serial In
P1.7
SPICLK
io3
Serial Clock
P3.6
IRQ1
io3
External Interrupt1
P3.7
IRQ2
io3
External Interrupt2
NRESET
NRESET
Reset
P1.4
LBD
io3
Low battery detect
P3.4
Modout
io3
Modulated output (TXEN tri-states)
P3.5
DI
io3
Digital (DI) / Analog (DI1) Data Input
DIREF
DIREF
io3
Analog Data Input Comparator External reference voltage
XFIN
XFIN
High frequency crystal input
XFOUT
XFOUT
High frequency crystal output
BXFOUT
BXFOUT
Buffered High Frequency Output
XSIN
XSIN
Slow frequency crystal input
XSOUT
XSOUT
Slow frequency crystal output
Vdd
Vdd
Digital Supply Voltage
Vss
Vss
Digital Ground
XVdd
Vdd
Digital Supply Voltage
XVss
Vss
Digital Ground
AVdd
AVdd
Analog Supply Voltage
Avss
AVss
Analog Ground
TST
TST
Test pin
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