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FS5502 Datasheet(PDF) 102 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 102 Page - NXP Semiconductors |
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102 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO Figure 44. Solder paste stencil 30.2 Component selection • SMPS input and output capacitors shall be chosen with low ESR (ceramic or MLCC type of capacitors). X7R ceramic type is preferred. Input decoupling capacitors shall be placed as close as possible to the device pin. Output capacitor voltage rating shall be selected to be 3x the voltage output value to minimize the DC bias degradation. • SMPS inductors shall be shielded with ISAT higher than maximum inductor peak current. 30.3 VPRE • Inductor charging and discharging current loop is designed as small as possible. • Input decoupling capacitors are placed close to the high-side drain transistor pin. • The boot strap capacitor is placed close to the device pin using wide and short track to connect to the external low-side drain transistor. FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 102 / 113 |
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