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FS5502 Datasheet(PDF) 103 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 103 Page - NXP Semiconductors |
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103 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO • PRE_GLS, PRE_GHS and PRE_SW tracks are wide and short and should not cross any sensitive signal (current sensing, for example). aaa-033211 L1 connection implementation Note : L2 is system ground. FS5502 L3 connection 1 2 3 4 • PRE_FB used as voltage feedback and current sense shall be connected to RSHUNT and routed as a pair with CSP. aaa-033212 layout as a pair do not cross any noisy signal FS5502 GND coil wire gound plane (and no sxxxx and pair) GND • The external transistor thermal shape should be in the range of 25 x 25 mm for optimum Rth. • The LFPAK56 application note can give better insight: http://assets.nexperia.com/ documents/application-note/AN10874.pdf FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 103 / 113 |
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