FS5502 datasheet(104/113 Pages) NXP

104 / 113 page

NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

30.4 VBUCKx

• Inductor charging and discharging current loop is designed as small as possible.

aaa-031038

BUCKx_IN

BUCKx_SW

switched path

direct path

Vpre (in)

BUCKx (out)

Cin: 4.7 µF cap located

near to BUCKx_IN

BUCKx_FB

• Input decoupling capacitors is placed close to BUCKx_IN pins.

• BUCK3_FB and BUCK3_INQ pins shall be tied to the same capacitor, VPRE output

capacitor depending on BUCK3_IN supply selected (in the blue path below, the coil is

parasitic from tracks). In the package, the coil is parasitic from the bonding.

aaa-033210

BUCK1

VPRE_FB

Vsup1/2

VPRE

BUCK1_IN

BUCK1_SW

clamp

BUCK3

BUCK3_INQ

VPRE

BUCK3

BUCK3_IN

BUCK3_SW

clamp

31 EMC compliance

The FS5502 EMC performance will be verified against BISS generic IC EMC test

specification version 2.0 from 07.2012 and FMC1278 electromagnetic compatibility

specification for electrical/electronic components and subsystems from 2016 with the

following specific conditions:

• Conducted emission: IEC 61967-4

– Global pins: VBAT (Vsup1 and Vsup2), WAKE1/2, 150 Ω method, 12-M level

– Local pins: VPRE, BUCK1/3, LDO1, 150 Ω method, 10-K level

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

104 / 113

FS5502 Datasheet(PDF) 104 Page - NXP Semiconductors

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