FS5502 datasheet(105/113 Pages) NXP

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NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

• Conducted immunity: IEC 62132-4

– Global pins: VBAT (Vsup1 and Vsup2), 36 dBm, Class A (no state change on RSTB,

PGOOD and all regulators in spec)

– Global pins: WAKE1, WAKE2, 30 dBm, Class A (no state change on RSTB, PGOOD

and all regulators in spec)

– Local pins: RSTB, PGOOD, VDDIO, VDDI2C, VBOS, 12 dBm, Class A (no state

change on RSTB, PGOOD and all regulators in spec)

– Supply pins: VPRE, BUCK1/3, LDO1, 12 dBm, Class A (no state change on RSTB,

PGOOD and all regulators in spec)

• Radiated emission: FMC1278 from July 2015

– Compliance with FMC1278 RE310 Level 2 requirement in Normal mode

• Radiated immunity: FMC1278 from July 2015

– Injection level per FMC1278 RI112 Level 2 requirement in Normal mode,

– No wake up when injecting FMC1278 RI112 Level 2 requirement in Standby mode

32 References

[1]

FS5502_PDTCALC[1] — VPRE compensation network calculation and power dissipation tool (Excel file)

[2]

FS5502_OTP_Mapping[1] — OTP programming configuration (Excel file)

[3]

FS5502_VPRE_Simplis_Model[1] — Simplis model for stability and transient simulations

[4]

Schematic[1] — Reference schematic in Cadence and PDF formats

[5]

Layout[1] — Reference layout in Cadence format

[6]

EVB[1] — Evaluation board (EVB)

[7]

FlexGUI[1] — Graphical user interface to be used with the EVB

[1]

Contact NXP sales representative.

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

105 / 113

FS5502 Datasheet(PDF) 105 Page - NXP Semiconductors